On Mon, 2021-07-19 at 13:34 +0800, Jacky Bai wrote:

On i.MX8ULP, for some of the PCCs, it has a peripheral SW RST bit
resides in the same registers as the clock controller. So add this
SW RST controller support alongs with the pcc clock initialization.

the reset and clock shared the same register, to avoid  accessing
the same register by reset control and clock control concurrently,
locking is necessary, so reuse the imx_ccm_lock spinlock to simplify
the code.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>

For the general idea of adding a reset controller in the clock driver,
you may add my 'Suggested-by: Liu Ying [off-list ref]', just like
the patch in our internal tree does.

Regards,
Liu Ying