Hi, Jitao:
On Mon, 2021-07-26 at 10:11 +0800, Jitao Shi wrote:
quoted hunk ↗ jump to hunk
Some bridge chip will shift screen when the dsi data does't ent at
the same time in line.
Signed-off-by: Jitao Shi <redacted>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index 8238a86686be..1c2f53f3ac3d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -19,6 +19,10 @@ Required properties:
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
+Optional properties:
+- force_dsi_end_without_null: Some bridge chip(ex. ANX7625) requires the
+ packets on lanes aligned at the end.
+
I think you should add this property in [1] because this limitation is
ANX7625's limitation.
[1]
Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
Regards,
CK
MIPI TX Configuration Module
============================