Hi Rob,

-----Original Message-----
From: Rob Herring <robh+dt@kernel.org>
Sent: Wednesday, June 16, 2021 2:39 AM
To: Thokala, Srikanth <srikanth.thokala@intel.com>
Cc: Lorenzo Pieralisi <redacted>; PCI <linux-
pci@vger.kernel.org>; devicetree@vger.kernel.org; Andy Shevchenko
[off-list ref]; Mark Gross [off-list ref];
Raja Subramanian, Lakshmi Bai [off-list ref];
Sangannavar, Mallikarjunappa [off-list ref];
Krzysztof Wilczynski [off-list ref]
Subject: Re: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay

On Mon, Jun 7, 2021 at 1:47 AM [off-list ref] wrote:

quoted

From: Srikanth Thokala <srikanth.thokala@intel.com>

Add driver for Intel Keem Bay SoC PCIe controller. This controller
is based on DesignWare PCIe core.

In Root Complex mode, only internal reference clock is possible for
Keem Bay A0. For Keem Bay B0, external reference clock can be used
and will be the default configuration. Currently, keembay_pcie_of_data
structure has one member. It will be expanded later to handle this
difference.

Endpoint mode link initialization is handled by the boot firmware.

Signed-off-by: Wan Ahmad Zainie <redacted>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com>
Reviewed-by: Krzysztof Wilczyński <redacted>
---
 MAINTAINERS                               |   7 +
 drivers/pci/controller/dwc/Kconfig        |  28 ++
 drivers/pci/controller/dwc/Makefile       |   1 +
 drivers/pci/controller/dwc/pcie-keembay.c | 451 ++++++++++++++++++++++
 4 files changed, 487 insertions(+)
 create mode 100644 drivers/pci/controller/dwc/pcie-keembay.c

Reviewed-by: Rob Herring <robh@kernel.org>

Thank you, Rob, for the "Reviewed-by".

Srikanth