On 30/06/2021 13:09, Chen-Yu Tsai wrote:

On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger [off-list ref] wrote:

quoted

On 30/06/2021 09:31, Chen-Yu Tsai wrote:

quoted

On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
[off-list ref] wrote:

quoted

On MT8195, tuner_en_reg is moved to register offest 0x0.
If we only judge by tuner_en_reg, it may lead to wrong address.
Add tuner_en_bit to the check condition. And it has been confirmed,
on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
clock square control.

Signed-off-by: Chun-Jie Chen <redacted>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Though you might want to consider converting these types of checks into feature
flags.

Yes I think adding a feature flag is the way to go. Luckily there are only a few
SoCs that will need updates at the same time.

I also see that the different clock modules are tied together using only clock
names written in the drivers, instead of clock references in the device tree.

Not sure I understand what you mean. Do you refer to something like [1]? That's
because the clock is probed by the DRM driver, as they share the same compatible
and IP block.

Regards,
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.13#n139

Unfortunately reworking this would likely require a lot more work. I previously
did a bit of internal reworking for the sunxi drivers. While not the same, I
think the plumbing required is comparable.

ChenYu