[PATCH v7 3/6] spi: rockchip: Set rx_fifo interrupt waterline base on transfer item
From: Jon Lin <hidden>
Date: 2021-06-15 03:26:38
Also in:
linux-arm-kernel, linux-rockchip, linux-spi, lkml
Subsystem:
arm/rockchip soc support, spi subsystem, the rest · Maintainers:
Heiko Stuebner, Mark Brown, Linus Torvalds
The error here is to calculate the width as 8 bits. In fact, 16 bits should be considered. Signed-off-by: Jon Lin <redacted> --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/spi/spi-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index bbeed3ae4ee1..0887b19ef3ad 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c@@ -540,8 +540,8 @@ static int rockchip_spi_config(struct rockchip_spi *rs, * interrupt exactly when the fifo is full doesn't seem to work, * so we need the strict inequality here */ - if (xfer->len < rs->fifo_len) - writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); + if ((xfer->len / rs->n_bytes) < rs->fifo_len) + writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); else writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
--
2.17.1