On Fri, Apr 02, 2021 at 02:50:49PM +0530, Nava kishore Manne wrote:
Adds support to handle FPGA/PL power domain. With this patch,
the PL power domain will be turned on before loading the bitstream
and turned off while removing/unloading the bitstream using overlays.
This can be achieved by adding the runtime PM support.
Signed-off-by: Nava kishore Manne <redacted>
---
drivers/fpga/of-fpga-region.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
quoted hunk ↗ jump to hunk
/**
@@ -411,9 +416,16 @@ static int of_fpga_region_probe(struct platform_device *pdev)
goto eprobe_mgr_put;
}
+ pm_runtime_enable(&pdev->dev);
+ ret = pm_runtime_get_sync(&pdev->dev);
+ if (ret < 0)
+ goto err_pm;
+
+ pm_runtime_put(&pdev->dev);
+
ret = fpga_region_register(region);
if (ret)
- goto eprobe_mgr_put;
+ goto err_pm;
Just a drive-by comment: you have PM usage counter imbalance here
(double put).
quoted hunk ↗ jump to hunk
of_platform_populate(np, fpga_region_of_match, NULL, ®ion->dev);
platform_set_drvdata(pdev, region);
@@ -422,6 +434,9 @@ static int of_fpga_region_probe(struct platform_device *pdev)
return 0;
+err_pm:
+ pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
eprobe_mgr_put:
fpga_mgr_put(mgr);
return ret;
Johan