[PATCH 4/4] arm64: dts: ti: k3-am642-evm/sk: Reserve some on-chip SRAM for R5Fs
From: Suman Anna <hidden>
Date: 2021-05-28 14:47:38
Also in:
linux-arm-kernel
Subsystem:
arm/texas instruments k3 architecture, the rest · Maintainers:
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Linus Torvalds
Reserve some portions of the MAIN domain on-chip SRAM for use by various R5F cores on AM642 EVM and SK boards. A bank (256 KB) each is reserved from the on-chip SRAM for each R5F core. This is done through specific child SRAM nodes in the board dts file. The memory regions are also assigned to each R5F remoteproc node using the sram property. The reserved SRAM banks are as follows for each core: Main R5FSS0 Core0 : OCSRAM1 Main R5FSS0 Core1 : OCSRAM2 Main R5FSS1 Core0 : OCSRAM3 Main R5FSS1 Core1 : OCSRAM4 Signed-off-by: Suman Anna <redacted> Signed-off-by: Ming Wei <redacted> --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 22 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 22 ++++++++++++++++++++++ 2 files changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 4d0b3f86525e..083df636d7ff 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts@@ -184,28 +184,50 @@ cpsw3g_phy3: ethernet-phy@3 { }; }; +&oc_sram { + main_r5fss0_core0_sram: r5f-sram@40000 { + reg = <0x40000 0x40000>; + }; + + main_r5fss0_core1_sram: r5f-sram@80000 { + reg = <0x80000 0x40000>; + }; + + main_r5fss1_core0_sram: r5f-sram@c0000 { + reg = <0xc0000 0x40000>; + }; + + main_r5fss1_core1_sram: r5f-sram@100000 { + reg = <0x100000 0x40000>; + }; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + sram = <&main_r5fss0_core0_sram>; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + sram = <&main_r5fss0_core1_sram>; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + sram = <&main_r5fss1_core0_sram>; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + sram = <&main_r5fss1_core1_sram>; }; &main_pmx0 {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 5891e6a05ddf..b388b3ca210a 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts@@ -387,26 +387,48 @@ &mailbox0_cluster7 { status = "disabled"; }; +&oc_sram { + main_r5fss0_core0_sram: r5f-sram@40000 { + reg = <0x40000 0x40000>; + }; + + main_r5fss0_core1_sram: r5f-sram@80000 { + reg = <0x80000 0x40000>; + }; + + main_r5fss1_core0_sram: r5f-sram@c0000 { + reg = <0xc0000 0x40000>; + }; + + main_r5fss1_core1_sram: r5f-sram@100000 { + reg = <0x100000 0x40000>; + }; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + sram = <&main_r5fss0_core0_sram>; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + sram = <&main_r5fss0_core1_sram>; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + sram = <&main_r5fss1_core0_sram>; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + sram = <&main_r5fss1_core1_sram>; };
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2.30.1