Thread (3 messages) flat view 3 messages, 2 authors, 2021-05-26
STALE1904d LANDED

Landed in mainline as 6b562738a22c on 2021-05-26.

[PATCH v4] dt-binding: mtd: nand: Document the cs-gpios property

From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: 2021-05-10 17:18:27
Subsystem: memory technology devices (mtd), open firmware and flattened device tree bindings, the rest · Maintainers: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds

To reach higher capacities, arrays of chips are now pretty common.
Unfortunately, most of the controllers have been designed a decade ago
and did not all anticipate the need for several chip-selects. The new
cs-gpios property allows to workaround this limitation by adding as many
GPIO chip-select as needed.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---

Resending only the binding patch of the series, with the following
changes requested by Rob:
* Fixed the coherency between cs-gpios and gpios-cs
* Added maxItems: 8 (this is a good enough value for most of the cases I
  guess, this can be increased later if needed).
* Adding maxItems: 8 lead to an error when checking the example,
  minItems: 8 had to be added as well to the schema to fix it, not sure
  this was expected or not.

 .../bindings/mtd/nand-controller.yaml          | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index 678b39952502..bd217e6f5018 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -38,6 +38,17 @@ properties:
 
   ranges: true
 
+  cs-gpios:
+    minItems: 1
+    maxItems: 8
+    description:
+      Array of chip-select available to the controller. The first
+      entries are a 1:1 mapping of the available chip-select on the
+      NAND controller (even if they are not used). As many additional
+      chip-select as needed may follow and should be phandles of GPIO
+      lines. 'reg' entries of the NAND chip subnodes become indexes of
+      this array when this property is present.
+
 patternProperties:
   "^nand@[a-f0-9]$":
     type: object
@@ -164,14 +175,19 @@ examples:
     nand-controller {
       #address-cells = <1>;
       #size-cells = <0>;
+      cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
 
       /* controller specific properties */
 
       nand@0 {
-        reg = <0>;
+        reg = <0>; /* Native CS */
         nand-use-soft-ecc-engine;
         nand-ecc-algo = "bch";
 
         /* controller specific properties */
       };
+
+      nand@1 {
+        reg = <1>; /* GPIO CS */
+      };
     };
-- 
2.27.0
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