Re: [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
From: Dong Aisheng <hidden>
Date: 2021-05-18 07:55:31
Also in:
linux-arm-kernel, lkml
On Tue, May 18, 2021 at 1:16 AM [off-list ref] wrote:
quoted hunk ↗ jump to hunk
From: Jacky Bai <ping.bai@nxp.com> Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added compared to i.MX8QXP. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <redacted> --- .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsidiff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi new file mode 100644 index 000000000000..640b43f5ae97 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi@@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +&ddr_subsys { + db_ipg_clk: clock-db-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;
fix lpcg index
+ clock-names = "ipg", "cnt";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+
+ db_pmu0_lpcg: clock-controller@5cae0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5cae0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&db_ipg_clk>, <&db_ipg_clk>;
+ bit-offset = <0 16>;fix lpcg index by using macro
+ clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +}; -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel