Hi Stephen,

On Wed, Mar 3, 2021 at 4:37 AM Stephen Boyd [off-list ref] wrote:

Quoting Shubhrajyoti Datta (2021-02-24 06:10:08)

quoted

On Fri, Feb 19, 2021 at 6:54 AM Stephen Boyd [off-list ref] wrote:

quoted

quoted

quoted

+
+  xlnx,speed-grade:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [1, 2, 3]
+    description:
+      Speed grade of the device.

A bit of explanation of what this describes would be welcome.

Don't forget that binding are not tied to any driver implementation,
these are supposed to be hardware description properties.

Would opp tables work for this?

This is the parameter is for speed of the fabric.

Ok. Yes or no? Is it configuring the speed of the fabric? Sounds like
assigned-clock-rates or assigned-interconnect-bandwidth or something
like that.

I do not think we could use opp tables.
Xilinx has products where we have partly FPGA and patrly PS(hardware
is not programmable) so the ip could be in PL
and the processor  in PS.

The speed grade influences a variety of timing parameters in the FPGA,
including fabric (slice), multiplier/DSP48x, BlockRAM, I/O, and other
resources parameters.

Basically the timing of the fabric is determined by it. Also we are
notifying the speed grade to the driver no configuration is done.
We are telling which speed-grade fabric we are running on.

 There is no correlation between these numbers. It is really a
relative metric of performance within a specific family.