Re: [PATCH v3 2/2] arm64: dts: qcom: sm8250: fix display nodes

On Thu, 11 Mar 2021 at 03:10, Bjorn Andersson
[off-list ref] wrote:

On Tue 16 Feb 15:14 CST 2021, Dmitry Baryshkov wrote:

quoted

Except for the compatible value changes:

Reviewed-by: Dmitry Baryshkov <redacted>

May I suggest to split the compatibility name changes into a separate
series from this patch (without it the patch stands a chance of being
accepted into the stable tree, if I'm not mistaken).

Please let me know what I should do with this patch.

I suggested splitting the compatibility settings, so that the fixes
can go into the stable branch. I can carve that out, if Jonathan does
not object.

Regards,
Bjorn

quoted

On Mon, 15 Feb 2021 at 19:27, Jonathan Marek [off-list ref] wrote:

quoted

Apply these fixes to the newly added sm8250 display ndoes
 - Use sm8250 compatibles instead of sdm845 compatibles
 - Remove "notused" interconnect (which apparently was blindly copied from
   my old patches)
 - Use dispcc node example from dt-bindings, removing clocks which aren't
   documented or used by the driver and fixing the region size.

Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek <redacted>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 31 +++++++---------------------
 1 file changed, 8 insertions(+), 23 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..693ac533f9b6 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi

@@ -2323,14 +2323,13 @@ usb_2_dwc3: dwc3@a800000 {
                };

                mdss: mdss@ae00000 {
-                       compatible = "qcom,sdm845-mdss";
+                       compatible = "qcom,sm8250-mdss";
                        reg = <0 0x0ae00000 0 0x1000>;
                        reg-names = "mdss";

-                       interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
-                                       <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
+                       interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
                                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
-                       interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+                       interconnect-names = "mdp0-mem", "mdp1-mem";

                        power-domains = <&dispcc MDSS_GDSC>;

@@ -2356,7 +2355,7 @@ mdss: mdss@ae00000 {
                        ranges;

                        mdss_mdp: mdp@ae01000 {
-                               compatible = "qcom,sdm845-dpu";
+                               compatible = "qcom,sm8250-dpu";
                                reg = <0 0x0ae01000 0 0x8f000>,
                                      <0 0x0aeb0000 0 0x2008>;
                                reg-names = "mdp", "vbif";

@@ -2580,7 +2579,7 @@ opp-358000000 {

                dispcc: clock-controller@af00000 {
                        compatible = "qcom,sm8250-dispcc";
-                       reg = <0 0x0af00000 0 0x20000>;
+                       reg = <0 0x0af00000 0 0x10000>;
                        mmcx-supply = <&mmcx_reg>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&dsi0_phy 0>,

@@ -2588,28 +2587,14 @@ dispcc: clock-controller@af00000 {
                                 <&dsi1_phy 0>,
                                 <&dsi1_phy 1>,
                                 <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <0>,
-                                <&sleep_clk>;
+                                <0>;
                        clock-names = "bi_tcxo",
                                      "dsi0_phy_pll_out_byteclk",
                                      "dsi0_phy_pll_out_dsiclk",
                                      "dsi1_phy_pll_out_byteclk",
                                      "dsi1_phy_pll_out_dsiclk",
-                                     "dp_link_clk_divsel_ten",
-                                     "dp_vco_divided_clk_src_mux",
-                                     "dptx1_phy_pll_link_clk",
-                                     "dptx1_phy_pll_vco_div_clk",
-                                     "dptx2_phy_pll_link_clk",
-                                     "dptx2_phy_pll_vco_div_clk",
-                                     "edp_phy_pll_link_clk",
-                                     "edp_phy_pll_vco_div_clk",
-                                     "sleep_clk";
+                                     "dp_phy_pll_link_clk",
+                                     "dp_phy_pll_vco_div_clk";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                        #power-domain-cells = <1>;
--

2.26.1

--
With best wishes
Dmitry

-- 
With best wishes
Dmitry