On Tue, Feb 09, 2021 at 10:46:59AM -0600, Rob Herring wrote:

On Mon, Jan 25, 2021 at 10:38:24AM +0100, Sascha Hauer wrote:

quoted

This adds support for an additional clock for the dwc2 core in case
there is another clock to the phy which must be enabled.

to the phy? 'clocks' is inputs to DWC2. Shouldn't there be a phy 
device/driver?

Maybe I should have said "from the phy". I have a USB3320 ULPI phy here
connected to the DWC2. The usual setup would look like this:

-----.    clk60M   .------------
DWC2 |<------------| USB3320 Phy
-----'             '------------

I don't think this clock is abstracted anywhere in this case, it's just
there and always enabled.

For reasons unknown to me our customer decided to not let the USB3320
generate the clock, but used an external clock generator instead, so
my setup looks like this:

        | SI5351a |
        '---------'
  clk60M_1 |  | clk60M_2
-----.     |  |    .------------
DWC2 |<----'  '--->| USB3320 Phy
-----'             '------------

The SI5351a is abstracted as a clock driver in Linux. Note that clk60M_1
and clk60M_2 are really two clocks which must both be enabled. clk60M_2
is handled by the phy driver (which is the usb-nop-xceiver in my case),
what I am trying to add here in this patch is support for clk60M_1.

Sascha

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