[PATCH 6/6] clk: qcom: gcc-sdm660: Add CLK_SET_RATE_PARENT where applicable
From: Konrad Dybcio <hidden>
Date: 2021-02-20 15:58:57
Also in:
linux-arm-msm, linux-clk, lkml, phone-devel
Subsystem:
arm/qualcomm mailing list, common clk framework, qualcomm clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Bjorn Andersson, Linus Torvalds
Some branch clocks should explicitly set this flag to make sure
they inherit their frequencies from the parent clock.
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Konrad Dybcio <redacted>
---
drivers/clk/qcom/gcc-sdm660.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index db2185c88b77..2c182936fc09 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c@@ -1606,6 +1606,7 @@ static struct clk_branch gcc_gpu_gpll0_clk = { "gpll0", }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, },
@@ -1623,6 +1624,7 @@ static struct clk_branch gcc_gpu_gpll0_div_clk = { "gpll0_early_div", }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, },
@@ -1672,6 +1674,7 @@ static struct clk_branch gcc_mmss_gpll0_clk = { "gpll0", }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, },
@@ -1689,6 +1692,7 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = { "gpll0_early_div", }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, },
--
2.30.1