Re: [PATCH v2 1/2] dt-bindings: display: bridge: Add documentation for SN65DSI84
From: Rob Herring <robh@kernel.org>
Date: 2021-02-04 17:42:07
Also in:
dri-devel, lkml
On Wed, Feb 03, 2021 at 12:42:55PM +0530, Jagan Teki wrote:
quoted hunk ↗ jump to hunk
SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from Texas Instruments. SN65DSI83, SN65DSI85 are variants of the same family of bridge controllers. Right now the bridge driver is supporting a single link, dual-link support requires to initiate I2C Channel B registers, so dt-bindings documented with single link LVDS. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v2: - none .../bindings/display/bridge/ti,sn65dsi84.yaml | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yamldiff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml new file mode 100644 index 000000000000..891382a76c1a --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml@@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi84.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI SN65DSI84 MIPI DSI to LVDS bridge bindings + +maintainers: + - Jagan Teki <jagan@amarulasolutions.com> + +description: | + The SN65DSI84 DSI to FlatLink bridge features a single channel MIPI D-PHY receiver + front-end configuration with 4 lanes per channel operating at 1 Gbps per lanes. + The bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and converts + the formatted video data stream to a FlatLink compatible LVDS output operating + at pixel clocks operating from 25 MHx to 154 MHz, offering a Dual-Link LVDS, + Single-Link LVDS interface with four data lanes per link. + + https://www.ti.com/product/SN65DSI84 + +properties: + compatible: + const: ti,sn65dsi84 + + reg: + maxItems: 1 + description: i2c address of the bridge, 0x2c
Just 'const: 0x2c' if that's the only valid address.
+ + enable-gpios: + maxItems: 1 + description: GPIO specifier for bridge enable pin (active high). + + ports: + type: object + description: + A node containing input and output port nodes with endpoint definitions + as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + DSI Input. The remote endpoint phandle should be a + reference to a valid mipi_dsi_host device node. + + port@1: + type: object + description: | + Video port for LVDS output (panel or connector).
This needs to use the graph.yaml schema. See the ones in drm-misc-next that are already converted.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&bridge_in>;
+ data-lanes = <0 1>;
+ };
+ };
+ };
+ };
+
+ i2c6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@2c {
+ compatible = "ti,sn65dsi84";
+ reg = <0x2c>;
+ enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+ };
+ };
--
2.25.1