Changes in V6:
- Rebased patches to usb-testing.
- Renamed to PATCH series instead of RFC.
- Checking for fs_descriptors instead of ss_descriptors for determining the
endpoint count for a particular configuration.
- Re-ordered patch series to fix patch dependencies.
Changes in V5:
- Added check_config() logic, which is used to communicate the number of EPs
used in a particular configuration. Based on this, the DWC3 gadget driver
has the ability to know the maximum number of eps utilized in all configs.
This helps reduce unnecessary allocation to unused eps, and will catch fifo
allocation issues at bind() time.
- Fixed variable declaration to single line per variable, and reverse xmas.
- Created a helper for fifo clearing, which is used by ep0.c
Changes in V4:
- Removed struct dwc3* as an argument for dwc3_gadget_resize_tx_fifos()
- Removed WARN_ON(1) in case we run out of fifo space
Changes in V3:
- Removed "Reviewed-by" tags
- Renamed series back to RFC
- Modified logic to ensure that fifo_size is reset if we pass the minimum
threshold. Tested with binding multiple FDs requesting 6 FIFOs.
Changes in V2:
- Modified TXFIFO resizing logic to ensure that each EP is reserved a
FIFO.
- Removed dev_dbg() prints and fixed typos from patches
- Added some more description on the dt-bindings commit message
Currently, there is no functionality to allow for resizing the TXFIFOs, and
relying on the HW default setting for the TXFIFO depth. In most cases, the
HW default is probably sufficient, but for USB compositions that contain
multiple functions that require EP bursting, the default settings
might not be enough. Also to note, the current SW will assign an EP to a
function driver w/o checking to see if the TXFIFO size for that particular
EP is large enough. (this is a problem if there are multiple HW defined
values for the TXFIFO size)
It is mentioned in the SNPS databook that a minimum of TX FIFO depth = 3
is required for an EP that supports bursting. Otherwise, there may be
frequent occurences of bursts ending. For high bandwidth functions,
such as data tethering (protocols that support data aggregation), mass
storage, and media transfer protocol (over FFS), the bMaxBurst value can be
large, and a bigger TXFIFO depth may prove to be beneficial in terms of USB
throughput. (which can be associated to system access latency, etc...) It
allows for a more consistent burst of traffic, w/o any interruptions, as
data is readily available in the FIFO.
With testing done using the mass storage function driver, the results show
that with a larger TXFIFO depth, the bandwidth increased significantly.
Test Parameters:
- Platform: Qualcomm SM8150
- bMaxBurst = 6
- USB req size = 256kB
- Num of USB reqs = 16
- USB Speed = Super-Speed
- Function Driver: Mass Storage (w/ ramdisk)
- Test Application: CrystalDiskMark
Results:
TXFIFO Depth = 3 max packets
Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------
Sequential|1 GB x |
Read |9 loops | 193.60
| | 195.86
| | 184.77
| | 193.60
-------------------------------------------
TXFIFO Depth = 6 max packets
Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------
Sequential|1 GB x |
Read |9 loops | 287.35
| | 304.94
| | 289.64
| | 293.61
-------------------------------------------
Wesley Cheng (4):
usb: gadget: udc: core: Introduce check_config to verify USB
configuration
usb: gadget: configfs: Check USB configuration before adding
usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
arm64: boot: dts: qcom: sm8150: Enable dynamic TX FIFO resize logic
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 +++++++++++++++++++++++++++++++++++
drivers/usb/gadget/configfs.c | 22 ++++
drivers/usb/gadget/udc/core.c | 9 ++
include/linux/usb/gadget.h | 2 +
8 files changed, 240 insertions(+)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Some UDCs may have constraints on how many high bandwidth endpoints it can
support in a certain configuration. This API allows for the composite
driver to pass down the total number of endpoints to the UDC so it can verify
it has the required resources to support the configuration.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/gadget/udc/core.c | 9 +++++++++
include/linux/usb/gadget.h | 2 ++
2 files changed, 11 insertions(+)
From: Jack Pham <hidden> Date: 2021-01-22 05:19:02
Hi Wesley,
On Thu, Jan 21, 2021 at 08:01:37PM -0800, Wesley Cheng wrote:
quoted hunk
Some UDCs may have constraints on how many high bandwidth endpoints it can
support in a certain configuration. This API allows for the composite
driver to pass down the total number of endpoints to the UDC so it can verify
it has the required resources to support the configuration.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/gadget/udc/core.c | 9 +++++++++
include/linux/usb/gadget.h | 2 ++
2 files changed, 11 insertions(+)
@@ -1003,6 +1003,15 @@ int usb_gadget_ep_match_desc(struct usb_gadget *gadget,}EXPORT_SYMBOL_GPL(usb_gadget_ep_match_desc);+intusb_gadget_check_config(structusb_gadget*gadget,unsignedlongep_map)
You should probably add a kernel-doc for this function.
Jack
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Wesley,
On Thu, Jan 21, 2021 at 08:01:37PM -0800, Wesley Cheng wrote:
quoted
Some UDCs may have constraints on how many high bandwidth endpoints it can
support in a certain configuration. This API allows for the composite
driver to pass down the total number of endpoints to the UDC so it can verify
it has the required resources to support the configuration.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/gadget/udc/core.c | 9 +++++++++
include/linux/usb/gadget.h | 2 ++
2 files changed, 11 insertions(+)
@@ -1003,6 +1003,15 @@ int usb_gadget_ep_match_desc(struct usb_gadget *gadget,}EXPORT_SYMBOL_GPL(usb_gadget_ep_match_desc);+intusb_gadget_check_config(structusb_gadget*gadget,unsignedlongep_map)
You should probably add a kernel-doc for this function.
Jack
Hi Jack,
Sure, I'll update a bit more about how this API can be used.
Thanks
Wesley Cheng
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
From: Alan Stern <stern@rowland.harvard.edu> Date: 2021-01-22 16:28:58
On Thu, Jan 21, 2021 at 08:01:37PM -0800, Wesley Cheng wrote:
Some UDCs may have constraints on how many high bandwidth endpoints it can
support in a certain configuration. This API allows for the composite
driver to pass down the total number of endpoints to the UDC so it can verify
it has the required resources to support the configuration.
Signed-off-by: Wesley Cheng <redacted>
On Thu, Jan 21, 2021 at 08:01:37PM -0800, Wesley Cheng wrote:
quoted
Some UDCs may have constraints on how many high bandwidth endpoints it can
support in a certain configuration. This API allows for the composite
driver to pass down the total number of endpoints to the UDC so it can verify
it has the required resources to support the configuration.
Signed-off-by: Wesley Cheng <redacted>
@@ -607,6 +608,7 @@ int usb_gadget_connect(struct usb_gadget *gadget);intusb_gadget_disconnect(structusb_gadget*gadget);intusb_gadget_deactivate(structusb_gadget*gadget);intusb_gadget_activate(structusb_gadget*gadget);+intusb_gadget_check_config(structusb_gadget*gadget,unsignedlongep_map);#elsestaticinlineintusb_gadget_frame_number(structusb_gadget*gadget){return0;}
Don't you also need an entry for the case where CONFIG_USB_GADGET isn't
enabled?
Alan Stern
Hi Alan,
Thanks for pointing that out. I missed that, and will add it to the
next rev.
Thanks
Wesley Cheng
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Enable the flexible TX FIFO resize logic on SM8150. Using a larger TX FIFO
SZ can help account for situations when system latency is greater than the
USB bus transmission latency.
Signed-off-by: Wesley Cheng <redacted>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
1 file changed, 1 insertion(+)
Ensure that the USB gadget is able to support the configuration being
added based on the number of endpoints required from all interfaces. This
is for accounting for any bandwidth or space limitations.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/gadget/configfs.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
@@ -616,6 +616,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)return-EINVAL;caseUSB_STATE_ADDRESS:+dwc3_gadget_clear_tx_fifos(dwc);+ret=dwc3_ep0_delegate_req(dwc,ctrl);/* if the cfg matches and the cfg is non zero */if(cfg&&(!ret||(ret==USB_GADGET_DELAYED_STATUS))){
@@ -615,6 +615,161 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)staticvoiddwc3_stop_active_transfer(structdwc3_ep*dep,boolforce,boolinterrupt);+staticintdwc3_gadget_calc_tx_fifo_size(structdwc3*dwc,intmult)+{+intmax_packet=1024;+intfifo_size;+intmdwidth;++mdwidth=DWC3_MDWIDTH(dwc->hwparams.hwparams0);+/* MDWIDTH is represented in bits, we need it in bytes */+mdwidth>>=3;++fifo_size=mult*((max_packet+mdwidth)/mdwidth)+1;+returnfifo_size;+}++voiddwc3_gadget_clear_tx_fifos(structdwc3*dwc)+{+structdwc3_ep*dep;+intfifo_depth;+intsize;+intnum;++if(!dwc->needs_fifo_resize)+return;++/* Read ep0IN related TXFIFO size */+dep=dwc->eps[1];+size=dwc3_readl(dwc->regs,DWC3_GTXFIFOSIZ(0));+if(DWC3_IP_IS(DWC31))+fifo_depth=DWC31_GTXFIFOSIZ_TXFDEP(size);+else+fifo_depth=DWC3_GTXFIFOSIZ_TXFDEP(size);++dwc->last_fifo_depth=fifo_depth;+/* Clear existing TXFIFO for all IN eps except ep0 */+for(num=3;num<min_t(int,dwc->num_eps,DWC3_ENDPOINTS_NUM);+num+=2){+dep=dwc->eps[num];+/* Don't change TXFRAMNUM on usb31 version */+size=DWC3_IP_IS(DWC31)?+dwc3_readl(dwc->regs,DWC3_GTXFIFOSIZ(num>>1))&+DWC31_GTXFIFOSIZ_TXFRAMNUM:0;++dwc3_writel(dwc->regs,DWC3_GTXFIFOSIZ(num>>1),size);+}+dwc->num_ep_resized=0;+}++/*+*dwc3_gadget_resize_tx_fifos-reallocatefifospacesforcurrentuse-case+*@dwc:pointertoourcontextstructure+*+*ThisfunctionwillabesteffortFIFOallocationinorder+*toimproveFIFOusageandthroughput,whilestillallowing+*ustoenableasmanyendpointsaspossible.+*+*Keepinmindthatthisoperationwillbehighlydependent+*ontheconfiguredsizeforRAM1-whichcontainsTxFifo-,+*theamountofendpointsenabledoncoreConsultanttool,and+*thewidthoftheMasterBus.+*+*Ingeneral,FIFOdepthsarerepresentedwiththefollowingequation:+*+*fifo_size=mult*((max_packet+mdwidth)/mdwidth+1)+1+*+*Conversionscanbedonetotheequationtoderivethenumberofpacketsthat+*willfittoaparticularFIFOsizevalue.+*/+staticintdwc3_gadget_resize_tx_fifos(structdwc3_ep*dep)+{+structdwc3*dwc=dep->dwc;+intfifo_0_start;+intram1_depth;+intfifo_size;+intmin_depth;+intnum_in_ep;+intremaining;+intmult=1;+intfifo;+inttmp;++if(!dwc->needs_fifo_resize)+return0;++/* resize IN endpoints except ep0 */+if(!usb_endpoint_dir_in(dep->endpoint.desc)||dep->number<=1)+return0;++ram1_depth=DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);++if((dep->endpoint.maxburst>1&&+usb_endpoint_xfer_bulk(dep->endpoint.desc))||+usb_endpoint_xfer_isoc(dep->endpoint.desc))+mult=3;++if(dep->endpoint.maxburst>6&&+usb_endpoint_xfer_bulk(dep->endpoint.desc)&&DWC3_IP_IS(DWC31))+mult=6;++/* FIFO size for a single buffer */+fifo=dwc3_gadget_calc_tx_fifo_size(dwc,1);++/* Calculate the number of remaining EPs w/o any FIFO */+num_in_ep=dwc->max_cfg_eps;+num_in_ep-=dwc->num_ep_resized;++/* Reserve at least one FIFO for the number of IN EPs */+min_depth=num_in_ep*(fifo+1);+remaining=ram1_depth-min_depth-dwc->last_fifo_depth;++/*+*We'vealreadyreserved1FIFOperEP,socheckwhatwecanfitin+*additiontoit.Ifthereisnotenoughremainingspace,allocate+*alltheremainingspacetotheEP.+*/+fifo_size=(mult-1)*fifo;+if(remaining<fifo_size){+if(remaining>0)+fifo_size=remaining;+else+fifo_size=0;+}++fifo_size+=fifo;+/* Last increment according to the TX FIFO size equation */+fifo_size++;++/* Check if TXFIFOs start at non-zero addr */+tmp=dwc3_readl(dwc->regs,DWC3_GTXFIFOSIZ(0));+fifo_0_start=DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);++fifo_size|=(fifo_0_start+(dwc->last_fifo_depth<<16));+if(DWC3_IP_IS(DWC31))+dwc->last_fifo_depth+=DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);+else+dwc->last_fifo_depth+=DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);++/* Check fifo size allocation doesn't exceed available RAM size. */+if(dwc->last_fifo_depth>=ram1_depth){+dev_err(dwc->dev,"Fifosize(%d) > RAM size(%d) %s depth:%d\n",+dwc->last_fifo_depth,ram1_depth,+dep->endpoint.name,fifo_size);+if(DWC3_IP_IS(DWC31))+fifo_size=DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);+else+fifo_size=DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);+dwc->last_fifo_depth-=fifo_size;+return-ENOMEM;+}++dwc3_writel(dwc->regs,DWC3_GTXFIFOSIZ(dep->number>>1),fifo_size);+dwc->num_ep_resized++;++return0;+}+/***__dwc3_gadget_ep_enable-initializesahwendpoint*@dep:endpointtobeinitialized
@@ -632,6 +787,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)intret;if(!(dep->flags&DWC3_EP_ENABLED)){+ret=dwc3_gadget_resize_tx_fifos(dep);+if(ret)+returnret;+ret=dwc3_gadget_start_config(dep);if(ret)returnret;
@@ -2418,6 +2577,7 @@ static int dwc3_gadget_stop(struct usb_gadget *g)spin_lock_irqsave(&dwc->lock,flags);dwc->gadget_driver=NULL;+dwc->max_cfg_eps=0;spin_unlock_irqrestore(&dwc->lock,flags);free_irq(dwc->irq_gadget,dwc->ev_buf);
@@ -2485,6 +2645,39 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)return0;}+staticintdwc3_gadget_check_config(structusb_gadget*g,unsignedlongep_map)+{+structdwc3*dwc=gadget_to_dwc(g);+unsignedlongin_ep_map;+intfifo_size=0;+intram1_depth;+intep_num;++if(!dwc->needs_fifo_resize)+return0;++/* Only interested in the IN endpoints */+in_ep_map=ep_map>>16;+ep_num=hweight_long(in_ep_map);++if(ep_num<=dwc->max_cfg_eps)+return0;++/* Update the max number of eps in the composition */+dwc->max_cfg_eps=ep_num;++fifo_size=dwc3_gadget_calc_tx_fifo_size(dwc,dwc->max_cfg_eps);+/* Based on the equation, increment by one for every ep */+fifo_size+=dwc->max_cfg_eps;++/* Check if we can fit a single fifo per endpoint */+ram1_depth=DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);+if(fifo_size>ram1_depth)+return-ENOMEM;++return0;+}+staticconststructusb_gadget_opsdwc3_gadget_ops={.get_frame=dwc3_gadget_get_frame,.wakeup=dwc3_gadget_wakeup,
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
Under what circumstances should we specify this? And in particular are
there scenarios (in the Qualcomm platforms) where this must not be set?
In particular, the composition can be changed in runtime, so should we
set this for all Qualcomm platforms?
And if that's the case, can we not just set it from the qcom driver?
Regards,
Bjorn
@@ -616,6 +616,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)return-EINVAL;caseUSB_STATE_ADDRESS:+dwc3_gadget_clear_tx_fifos(dwc);+ret=dwc3_ep0_delegate_req(dwc,ctrl);/* if the cfg matches and the cfg is non zero */if(cfg&&(!ret||(ret==USB_GADGET_DELAYED_STATUS))){
@@ -615,6 +615,161 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)staticvoiddwc3_stop_active_transfer(structdwc3_ep*dep,boolforce,boolinterrupt);+staticintdwc3_gadget_calc_tx_fifo_size(structdwc3*dwc,intmult)+{+intmax_packet=1024;+intfifo_size;+intmdwidth;++mdwidth=DWC3_MDWIDTH(dwc->hwparams.hwparams0);+/* MDWIDTH is represented in bits, we need it in bytes */+mdwidth>>=3;++fifo_size=mult*((max_packet+mdwidth)/mdwidth)+1;+returnfifo_size;+}++voiddwc3_gadget_clear_tx_fifos(structdwc3*dwc)+{+structdwc3_ep*dep;+intfifo_depth;+intsize;+intnum;++if(!dwc->needs_fifo_resize)+return;++/* Read ep0IN related TXFIFO size */+dep=dwc->eps[1];+size=dwc3_readl(dwc->regs,DWC3_GTXFIFOSIZ(0));+if(DWC3_IP_IS(DWC31))+fifo_depth=DWC31_GTXFIFOSIZ_TXFDEP(size);+else+fifo_depth=DWC3_GTXFIFOSIZ_TXFDEP(size);++dwc->last_fifo_depth=fifo_depth;+/* Clear existing TXFIFO for all IN eps except ep0 */+for(num=3;num<min_t(int,dwc->num_eps,DWC3_ENDPOINTS_NUM);+num+=2){+dep=dwc->eps[num];+/* Don't change TXFRAMNUM on usb31 version */+size=DWC3_IP_IS(DWC31)?+dwc3_readl(dwc->regs,DWC3_GTXFIFOSIZ(num>>1))&+DWC31_GTXFIFOSIZ_TXFRAMNUM:0;++dwc3_writel(dwc->regs,DWC3_GTXFIFOSIZ(num>>1),size);+}+dwc->num_ep_resized=0;+}++/*+*dwc3_gadget_resize_tx_fifos-reallocatefifospacesforcurrentuse-case+*@dwc:pointertoourcontextstructure+*+*ThisfunctionwillabesteffortFIFOallocationinorder+*toimproveFIFOusageandthroughput,whilestillallowing+*ustoenableasmanyendpointsaspossible.+*+*Keepinmindthatthisoperationwillbehighlydependent+*ontheconfiguredsizeforRAM1-whichcontainsTxFifo-,+*theamountofendpointsenabledoncoreConsultanttool,and+*thewidthoftheMasterBus.+*+*Ingeneral,FIFOdepthsarerepresentedwiththefollowingequation:+*+*fifo_size=mult*((max_packet+mdwidth)/mdwidth+1)+1+*+*Conversionscanbedonetotheequationtoderivethenumberofpacketsthat+*willfittoaparticularFIFOsizevalue.+*/+staticintdwc3_gadget_resize_tx_fifos(structdwc3_ep*dep)+{+structdwc3*dwc=dep->dwc;+intfifo_0_start;+intram1_depth;+intfifo_size;+intmin_depth;+intnum_in_ep;+intremaining;+intmult=1;+intfifo;+inttmp;++if(!dwc->needs_fifo_resize)+return0;++/* resize IN endpoints except ep0 */+if(!usb_endpoint_dir_in(dep->endpoint.desc)||dep->number<=1)+return0;++ram1_depth=DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);++if((dep->endpoint.maxburst>1&&+usb_endpoint_xfer_bulk(dep->endpoint.desc))||+usb_endpoint_xfer_isoc(dep->endpoint.desc))+mult=3;++if(dep->endpoint.maxburst>6&&+usb_endpoint_xfer_bulk(dep->endpoint.desc)&&DWC3_IP_IS(DWC31))+mult=6;++/* FIFO size for a single buffer */+fifo=dwc3_gadget_calc_tx_fifo_size(dwc,1);++/* Calculate the number of remaining EPs w/o any FIFO */+num_in_ep=dwc->max_cfg_eps;+num_in_ep-=dwc->num_ep_resized;++/* Reserve at least one FIFO for the number of IN EPs */+min_depth=num_in_ep*(fifo+1);+remaining=ram1_depth-min_depth-dwc->last_fifo_depth;++/*+*We'vealreadyreserved1FIFOperEP,socheckwhatwecanfitin+*additiontoit.Ifthereisnotenoughremainingspace,allocate+*alltheremainingspacetotheEP.+*/+fifo_size=(mult-1)*fifo;+if(remaining<fifo_size){+if(remaining>0)+fifo_size=remaining;+else+fifo_size=0;+}++fifo_size+=fifo;+/* Last increment according to the TX FIFO size equation */+fifo_size++;++/* Check if TXFIFOs start at non-zero addr */+tmp=dwc3_readl(dwc->regs,DWC3_GTXFIFOSIZ(0));+fifo_0_start=DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);++fifo_size|=(fifo_0_start+(dwc->last_fifo_depth<<16));+if(DWC3_IP_IS(DWC31))+dwc->last_fifo_depth+=DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);+else+dwc->last_fifo_depth+=DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);++/* Check fifo size allocation doesn't exceed available RAM size. */+if(dwc->last_fifo_depth>=ram1_depth){+dev_err(dwc->dev,"Fifosize(%d) > RAM size(%d) %s depth:%d\n",+dwc->last_fifo_depth,ram1_depth,+dep->endpoint.name,fifo_size);+if(DWC3_IP_IS(DWC31))+fifo_size=DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);+else+fifo_size=DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);+dwc->last_fifo_depth-=fifo_size;+return-ENOMEM;+}++dwc3_writel(dwc->regs,DWC3_GTXFIFOSIZ(dep->number>>1),fifo_size);+dwc->num_ep_resized++;++return0;+}+/***__dwc3_gadget_ep_enable-initializesahwendpoint*@dep:endpointtobeinitialized
@@ -632,6 +787,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)intret;if(!(dep->flags&DWC3_EP_ENABLED)){+ret=dwc3_gadget_resize_tx_fifos(dep);+if(ret)+returnret;+ret=dwc3_gadget_start_config(dep);if(ret)returnret;
@@ -2418,6 +2577,7 @@ static int dwc3_gadget_stop(struct usb_gadget *g)spin_lock_irqsave(&dwc->lock,flags);dwc->gadget_driver=NULL;+dwc->max_cfg_eps=0;spin_unlock_irqrestore(&dwc->lock,flags);free_irq(dwc->irq_gadget,dwc->ev_buf);
@@ -2485,6 +2645,39 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)return0;}+staticintdwc3_gadget_check_config(structusb_gadget*g,unsignedlongep_map)+{+structdwc3*dwc=gadget_to_dwc(g);+unsignedlongin_ep_map;+intfifo_size=0;+intram1_depth;+intep_num;++if(!dwc->needs_fifo_resize)+return0;++/* Only interested in the IN endpoints */+in_ep_map=ep_map>>16;+ep_num=hweight_long(in_ep_map);++if(ep_num<=dwc->max_cfg_eps)+return0;++/* Update the max number of eps in the composition */+dwc->max_cfg_eps=ep_num;++fifo_size=dwc3_gadget_calc_tx_fifo_size(dwc,dwc->max_cfg_eps);+/* Based on the equation, increment by one for every ep */+fifo_size+=dwc->max_cfg_eps;++/* Check if we can fit a single fifo per endpoint */+ram1_depth=DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);+if(fifo_size>ram1_depth)+return-ENOMEM;++return0;+}+staticconststructusb_gadget_opsdwc3_gadget_ops={.get_frame=dwc3_gadget_get_frame,.wakeup=dwc3_gadget_wakeup,
Under what circumstances should we specify this? And in particular are
there scenarios (in the Qualcomm platforms) where this must not be set?
The TXFIFO dynamic allocation is actually a feature within the DWC3
controller, and isn't specifically for QCOM based platforms. It won't
do any harm functionally if this flag is not set, as this is meant for
enhancing performance/bandwidth.
In particular, the composition can be changed in runtime, so should we
set this for all Qualcomm platforms?
Ideally yes, if we want to increase bandwith for situations where SS
endpoint bursting is set to a higher value.
And if that's the case, can we not just set it from the qcom driver?
Since this is a common DWC3 core feature, I think it would make more
sense to have it in DWC3 core instead of a vendor's DWC3 glue driver.
Thanks
Wesley Cheng
Regards,
Bjorn
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Under what circumstances should we specify this? And in particular are
there scenarios (in the Qualcomm platforms) where this must not be set?
The TXFIFO dynamic allocation is actually a feature within the DWC3
controller, and isn't specifically for QCOM based platforms. It won't
do any harm functionally if this flag is not set, as this is meant for
enhancing performance/bandwidth.
quoted
In particular, the composition can be changed in runtime, so should we
set this for all Qualcomm platforms?
Ideally yes, if we want to increase bandwith for situations where SS
endpoint bursting is set to a higher value.
quoted
And if that's the case, can we not just set it from the qcom driver?
Since this is a common DWC3 core feature, I think it would make more
sense to have it in DWC3 core instead of a vendor's DWC3 glue driver.
I don't have any objections to implementing it in the core driver, but
my question is can we just skip the DT binding and just enable it from
the vendor driver?
Regards,
Bjorn
Under what circumstances should we specify this? And in particular are
there scenarios (in the Qualcomm platforms) where this must not be set?
The TXFIFO dynamic allocation is actually a feature within the DWC3
controller, and isn't specifically for QCOM based platforms. It won't
do any harm functionally if this flag is not set, as this is meant for
enhancing performance/bandwidth.
quoted
In particular, the composition can be changed in runtime, so should we
set this for all Qualcomm platforms?
Ideally yes, if we want to increase bandwith for situations where SS
endpoint bursting is set to a higher value.
quoted
And if that's the case, can we not just set it from the qcom driver?
Since this is a common DWC3 core feature, I think it would make more
sense to have it in DWC3 core instead of a vendor's DWC3 glue driver.
I don't have any objections to implementing it in the core driver, but
my question is can we just skip the DT binding and just enable it from
the vendor driver?
Regards,
Bjorn
Hi Bjorn,
I see. I think there are some designs which don't have a DWC3 glue
driver, so assuming there may be other platforms using this, there may
not always be a vendor driver to set this.
Thanks
Wesley Cheng
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Under what circumstances should we specify this? And in particular are
there scenarios (in the Qualcomm platforms) where this must not be set?
The TXFIFO dynamic allocation is actually a feature within the DWC3
controller, and isn't specifically for QCOM based platforms. It won't
do any harm functionally if this flag is not set, as this is meant for
enhancing performance/bandwidth.
quoted
In particular, the composition can be changed in runtime, so should we
set this for all Qualcomm platforms?
Ideally yes, if we want to increase bandwith for situations where SS
endpoint bursting is set to a higher value.
quoted
And if that's the case, can we not just set it from the qcom driver?
Since this is a common DWC3 core feature, I think it would make more
sense to have it in DWC3 core instead of a vendor's DWC3 glue driver.
I don't have any objections to implementing it in the core driver, but
my question is can we just skip the DT binding and just enable it from
the vendor driver?
Regards,
Bjorn
Hi Bjorn,
I see. I think there are some designs which don't have a DWC3 glue
driver, so assuming there may be other platforms using this, there may
not always be a vendor driver to set this.
You mean that there are implementations of dwc3 without an associated
glue driver that haven't yet realized that they need this feature?
I would suggest then that we implement the core code necessary, we
enable it from the Qualcomm glue layer and when someone realize that
they need this without a glue driver it's going to be trivial to add the
DT binding.
The alternative is that we're lugging around a requirement to specify
this property in all past, present and future Qualcomm dts files - and
then we'll need to hard code it for ACPI anyways.
Regards,
Bjorn
Under what circumstances should we specify this? And in particular are
there scenarios (in the Qualcomm platforms) where this must not be set?
The TXFIFO dynamic allocation is actually a feature within the DWC3
controller, and isn't specifically for QCOM based platforms. It won't
do any harm functionally if this flag is not set, as this is meant for
enhancing performance/bandwidth.
quoted
In particular, the composition can be changed in runtime, so should we
set this for all Qualcomm platforms?
Ideally yes, if we want to increase bandwith for situations where SS
endpoint bursting is set to a higher value.
quoted
And if that's the case, can we not just set it from the qcom driver?
Since this is a common DWC3 core feature, I think it would make more
sense to have it in DWC3 core instead of a vendor's DWC3 glue driver.
I don't have any objections to implementing it in the core driver, but
my question is can we just skip the DT binding and just enable it from
the vendor driver?
Regards,
Bjorn
Hi Bjorn,
I see. I think there are some designs which don't have a DWC3 glue
driver, so assuming there may be other platforms using this, there may
not always be a vendor driver to set this.
You mean that there are implementations of dwc3 without an associated
glue driver that haven't yet realized that they need this feature?
I would suggest then that we implement the core code necessary, we
enable it from the Qualcomm glue layer and when someone realize that
they need this without a glue driver it's going to be trivial to add the
DT binding.
quoted
The alternative is that we're lugging around a requirement to specify
this property in all past, present and future Qualcomm dts files - and
then we'll need to hard code it for ACPI anyways.
Hi Bjorn,
Can we utilize the of_add_property() call to add the "tx-fifo-resize"
property from the dwc3_qcom_register_core() API? That way at least the
above concern would be addressed.
I'm not too familiar with the ACPI design, but I do see that the
dwc3-qcom does have an array carrying some DWC3 core properties. Looks
like we can add the tx-fifo-resize property here too.
static const struct property_entry dwc3_qcom_acpi_properties[] = {
PROPERTY_ENTRY_STRING("dr_mode", "host"),
{}
};
Thanks
Wesley Cheng
Regards,
Bjorn
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
@@ -616,6 +616,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)return-EINVAL;caseUSB_STATE_ADDRESS:+dwc3_gadget_clear_tx_fifos(dwc);+ret=dwc3_ep0_delegate_req(dwc,ctrl);/* if the cfg matches and the cfg is non zero */if(cfg&&(!ret||(ret==USB_GADGET_DELAYED_STATUS))){
@@ -615,6 +615,161 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)staticvoiddwc3_stop_active_transfer(structdwc3_ep*dep,boolforce,boolinterrupt);+staticintdwc3_gadget_calc_tx_fifo_size(structdwc3*dwc,intmult)
Can you document what this function does?
+{
+ int max_packet = 1024;
Maybe you can also document why you chose 1024 (e.g. applicable to
Enhanced SuperSpeed only?).
+ int fifo_size;
+ int mdwidth;
+
+ mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* MDWIDTH is represented in bits, we need it in bytes */
+ mdwidth >>= 3;
mdwidth for DWC32 requires to read hwparams6 for the upper 2 significant
bits. Can we add a check for DWC32 also? You can check how we're doing
it now in the current code.
+
+ fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
+ return fifo_size;
+}
+
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
+{
+ struct dwc3_ep *dep;
+ int fifo_depth;
+ int size;
+ int num;
+
+ if (!dwc->needs_fifo_resize)
+ return;
+
+ /* Read ep0IN related TXFIFO size */
+ dep = dwc->eps[1];
+ size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ if (DWC3_IP_IS(DWC31))
+ fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+ else
+ fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
The driver handles 3 IPs. Getting the fifo depth for DWC32 is the same
as DWC31. So the condition should be
if (DWC3_IP_IS(DWC3))
fifo_depth = ...
else
fifo_depth = ...
+
+ dwc->last_fifo_depth = fifo_depth;
+ /* Clear existing TXFIFO for all IN eps except ep0 */
+ for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
+ num += 2) {
+ dep = dwc->eps[num];
+ /* Don't change TXFRAMNUM on usb31 version */
+ size = DWC3_IP_IS(DWC31) ?
+ dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
+ DWC31_GTXFIFOSIZ_TXFRAMNUM : 0;
+
Same here. Check for DWC32.
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
+ }
+ dwc->num_ep_resized = 0;
+}
+
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+ struct dwc3 *dwc = dep->dwc;
+ int fifo_0_start;
+ int ram1_depth;
+ int fifo_size;
+ int min_depth;
+ int num_in_ep;
+ int remaining;
+ int mult = 1;
+ int fifo;
+ int tmp;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
Maybe add a condition to check for Enhanced SuperSpeed only?
+
+ /* resize IN endpoints except ep0 */
+ if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+ return 0;
+
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+
+ if ((dep->endpoint.maxburst > 1 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
+ usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ mult = 3;
+
+ if (dep->endpoint.maxburst > 6 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
+ mult = 6;
You checked maxburst > 1 for isoc, but not when maxburst > 6. Why?
Also, "mult" is the term we usually use for isoc endpoints. Applying it
to bulk is confusing here.
How did we decide on 3 and 6? Are they arbitrary?
+
+ /* FIFO size for a single buffer */
+ fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
+
+ /* Calculate the number of remaining EPs w/o any FIFO */
+ num_in_ep = dwc->max_cfg_eps;
+ num_in_ep -= dwc->num_ep_resized;
+
+ /* Reserve at least one FIFO for the number of IN EPs */
+ min_depth = num_in_ep * (fifo + 1);
+ remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
Can "remaining" be a negative value? If so, I think it's clearer if you do
remaining = max_t(int, 0, remaining);
+
+ /*
+ * We've already reserved 1 FIFO per EP, so check what we can fit in
+ * addition to it. If there is not enough remaining space, allocate
+ * all the remaining space to the EP.
+ */
+ fifo_size = (mult - 1) * fifo;
+ if (remaining < fifo_size) {
+ if (remaining > 0)
+ fifo_size = remaining;
+ else
+ fifo_size = 0;
Then use this condition instead:
if (remaining < fifo_size)
fifo_size = remaining;
+ }
+
+ fifo_size += fifo;
+ /* Last increment according to the TX FIFO size equation */
+ fifo_size++;
+
+ /* Check if TXFIFOs start at non-zero addr */
+ tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+ fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+ if (DWC3_IP_IS(DWC31))
+ dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+ else
+ dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
@@ -632,6 +787,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) int ret; if (!(dep->flags & DWC3_EP_ENABLED)) {+ ret = dwc3_gadget_resize_tx_fifos(dep);+ if (ret)+ return ret;+ ret = dwc3_gadget_start_config(dep); if (ret) return ret;
@@ -2485,6 +2645,39 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) return 0; }+static int dwc3_gadget_check_config(struct usb_gadget *g, unsigned long ep_map)
What's in ep_map? Can you document more to help with the review?
Thanks,
Thinh
quoted hunk
+{
+ struct dwc3 *dwc = gadget_to_dwc(g);
+ unsigned long in_ep_map;
+ int fifo_size = 0;
+ int ram1_depth;
+ int ep_num;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
+
+ /* Only interested in the IN endpoints */
+ in_ep_map = ep_map >> 16;
+ ep_num = hweight_long(in_ep_map);
+
+ if (ep_num <= dwc->max_cfg_eps)
+ return 0;
+
+ /* Update the max number of eps in the composition */
+ dwc->max_cfg_eps = ep_num;
+
+ fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
+ /* Based on the equation, increment by one for every ep */
+ fifo_size += dwc->max_cfg_eps;
+
+ /* Check if we can fit a single fifo per endpoint */
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+ if (fifo_size > ram1_depth)
+ return -ENOMEM;
+
+ return 0;
+}
+
static const struct usb_gadget_ops dwc3_gadget_ops = {
.get_frame = dwc3_gadget_get_frame,
.wakeup = dwc3_gadget_wakeup,
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
@@ -616,6 +616,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)return-EINVAL;caseUSB_STATE_ADDRESS:+dwc3_gadget_clear_tx_fifos(dwc);+ret=dwc3_ep0_delegate_req(dwc,ctrl);/* if the cfg matches and the cfg is non zero */if(cfg&&(!ret||(ret==USB_GADGET_DELAYED_STATUS))){
@@ -615,6 +615,161 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)staticvoiddwc3_stop_active_transfer(structdwc3_ep*dep,boolforce,boolinterrupt);+staticintdwc3_gadget_calc_tx_fifo_size(structdwc3*dwc,intmult)
Can you document what this function does?
Will do.
quoted
+{
+ int max_packet = 1024;
Maybe you can also document why you chose 1024 (e.g. applicable to
Enhanced SuperSpeed only?).
Sure. Its basically applicable for SS and isoc (hs/ss) use cases since
max packet size is 1024 in both cases.
quoted
+ int fifo_size;
+ int mdwidth;
+
+ mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* MDWIDTH is represented in bits, we need it in bytes */
+ mdwidth >>= 3;
mdwidth for DWC32 requires to read hwparams6 for the upper 2 significant
bits. Can we add a check for DWC32 also? You can check how we're doing
it now in the current code.
Sure. I'll make sure to get the correct registers for the DWC32 case.
quoted
+
+ fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
+ return fifo_size;
+}
+
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
+{
+ struct dwc3_ep *dep;
+ int fifo_depth;
+ int size;
+ int num;
+
+ if (!dwc->needs_fifo_resize)
+ return;
+
+ /* Read ep0IN related TXFIFO size */
+ dep = dwc->eps[1];
+ size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ if (DWC3_IP_IS(DWC31))
+ fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+ else
+ fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
The driver handles 3 IPs. Getting the fifo depth for DWC32 is the same
as DWC31. So the condition should be
if (DWC3_IP_IS(DWC3))
fifo_depth = ...
else
fifo_depth = ...
Understood.
quoted
+
+ dwc->last_fifo_depth = fifo_depth;
+ /* Clear existing TXFIFO for all IN eps except ep0 */
+ for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
+ num += 2) {
+ dep = dwc->eps[num];
+ /* Don't change TXFRAMNUM on usb31 version */
+ size = DWC3_IP_IS(DWC31) ?
+ dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
+ DWC31_GTXFIFOSIZ_TXFRAMNUM : 0;
+
Same here. Check for DWC32.
quoted
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
+ }
+ dwc->num_ep_resized = 0;
+}
+
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+ struct dwc3 *dwc = dep->dwc;
+ int fifo_0_start;
+ int ram1_depth;
+ int fifo_size;
+ int min_depth;
+ int num_in_ep;
+ int remaining;
+ int mult = 1;
+ int fifo;
+ int tmp;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
Maybe add a condition to check for Enhanced SuperSpeed only?
Since this logic applies for isoc endpoints as well in high speed mode,
for high bandwidth use cases, we can't limit it to SS only.
quoted
+
+ /* resize IN endpoints except ep0 */
+ if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+ return 0;
+
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+
+ if ((dep->endpoint.maxburst > 1 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
+ usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ mult = 3;
+
+ if (dep->endpoint.maxburst > 6 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
+ mult = 6;
You checked maxburst > 1 for isoc, but not when maxburst > 6. Why?
Also, "mult" is the term we usually use for isoc endpoints. Applying it
to bulk is confusing here.
Ok, let me rename it to something else that makes more sense. The isoc
endpoint check was targeted for mainly high-speed high bandwidth isoc
use cases, and I don't believe our results improved with a larger fifo
allocation, ie 6. (refer to below)
How did we decide on 3 and 6? Are they arbitrary?
So actually in the databook, they have some recommendations for TXFIFO
sizes to use in "Table 4-3 Device Config Parameters." It mentions that
for burst capable endpoints to have a fifo size to fit at least 3
packets of maxpacket size.
There's also "Chapter 3 Cache, FIFO RAMs, and Bandwidth Requirements,"
which goes over a lot of optimizations that could be done based off your
system's overall latency. The sizes were chosen after we ran our peak
throughput and performance testing on our devices, and these values
netted the best throughput while also allowing enough fifo space for our
other USB endpoints. Also, there's going to be a limit on how much
improvement you see with respects to increasing the fifo size, since
your system will eventually be able to pull data out of the internal
fifo faster than it is being filled.
quoted
+
+ /* FIFO size for a single buffer */
+ fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
+
+ /* Calculate the number of remaining EPs w/o any FIFO */
+ num_in_ep = dwc->max_cfg_eps;
+ num_in_ep -= dwc->num_ep_resized;
+
+ /* Reserve at least one FIFO for the number of IN EPs */
+ min_depth = num_in_ep * (fifo + 1);
+ remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
Can "remaining" be a negative value? If so, I think it's clearer if you do
remaining = max_t(int, 0, remaining);
Sure.
quoted
+
+ /*
+ * We've already reserved 1 FIFO per EP, so check what we can fit in
+ * addition to it. If there is not enough remaining space, allocate
+ * all the remaining space to the EP.
+ */
+ fifo_size = (mult - 1) * fifo;
+ if (remaining < fifo_size) {
+ if (remaining > 0)
+ fifo_size = remaining;
+ else
+ fifo_size = 0;
Then use this condition instead:
if (remaining < fifo_size)
fifo_size = remaining;
quoted
+ }
+
+ fifo_size += fifo;
+ /* Last increment according to the TX FIFO size equation */
+ fifo_size++;
+
+ /* Check if TXFIFOs start at non-zero addr */
+ tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+ fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+ if (DWC3_IP_IS(DWC31))
+ dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+ else
+ dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
@@ -632,6 +787,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) int ret; if (!(dep->flags & DWC3_EP_ENABLED)) {+ ret = dwc3_gadget_resize_tx_fifos(dep);+ if (ret)+ return ret;+ ret = dwc3_gadget_start_config(dep); if (ret) return ret;
@@ -2485,6 +2645,39 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) return 0; }+static int dwc3_gadget_check_config(struct usb_gadget *g, unsigned long ep_map)
What's in ep_map? Can you document more to help with the review?
Yeah, I will add some more comments. Just to explain here briefly, this
check config callback is to address the concern pointed out by Felipe
where we could run out of txfifo memory while our USB composition is
being enabled. This would lead to an enumerated device, with
non-functioning endpoints.
The check config will be called during the function driver bind stage
(before we enumerate), and ep_map carries the number of endpoints (both
in and out) being used in a particular configuration. With this
information, the logic will ensure that there is enough txfifo space for
at least 1 fifo per endpoint. If not, we can catch the failure at the
composition bind stages. (although it would be odd to see a DWC3
controller with not enough txfifo ram for 1 fifo per ep) The point at
which we actually resize the fifo allocations, will always check to make
sure that there is enough fifo space for the remaining endpoints after
every resize.
Thanks
Wesley Cheng
Thanks,
Thinh
quoted
+{
+ struct dwc3 *dwc = gadget_to_dwc(g);
+ unsigned long in_ep_map;
+ int fifo_size = 0;
+ int ram1_depth;
+ int ep_num;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
+
+ /* Only interested in the IN endpoints */
+ in_ep_map = ep_map >> 16;
+ ep_num = hweight_long(in_ep_map);
+
+ if (ep_num <= dwc->max_cfg_eps)
+ return 0;
+
+ /* Update the max number of eps in the composition */
+ dwc->max_cfg_eps = ep_num;
+
+ fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
+ /* Based on the equation, increment by one for every ep */
+ fifo_size += dwc->max_cfg_eps;
+
+ /* Check if we can fit a single fifo per endpoint */
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+ if (fifo_size > ram1_depth)
+ return -ENOMEM;
+
+ return 0;
+}
+
static const struct usb_gadget_ops dwc3_gadget_ops = {
.get_frame = dwc3_gadget_get_frame,
.wakeup = dwc3_gadget_wakeup,
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
@@ -616,6 +616,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)return-EINVAL;caseUSB_STATE_ADDRESS:+dwc3_gadget_clear_tx_fifos(dwc);+ret=dwc3_ep0_delegate_req(dwc,ctrl);/* if the cfg matches and the cfg is non zero */if(cfg&&(!ret||(ret==USB_GADGET_DELAYED_STATUS))){
@@ -615,6 +615,161 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)staticvoiddwc3_stop_active_transfer(structdwc3_ep*dep,boolforce,boolinterrupt);+staticintdwc3_gadget_calc_tx_fifo_size(structdwc3*dwc,intmult)
Can you document what this function does?
Will do.
quoted
quoted
+{
+ int max_packet = 1024;
Maybe you can also document why you chose 1024 (e.g. applicable to
Enhanced SuperSpeed only?).
Sure. Its basically applicable for SS and isoc (hs/ss) use cases since
max packet size is 1024 in both cases.
Highspeed bulk MPS is 512. Fullspeed varies more (bulk max MPS is 64 and
isoc is 1023).
However, we can keep it simple with 1024 as if it's ok to over estimate.
Just need to note that here.
quoted
quoted
+ int fifo_size;
+ int mdwidth;
+
+ mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* MDWIDTH is represented in bits, we need it in bytes */
+ mdwidth >>= 3;
mdwidth for DWC32 requires to read hwparams6 for the upper 2 significant
bits. Can we add a check for DWC32 also? You can check how we're doing
it now in the current code.
Sure. I'll make sure to get the correct registers for the DWC32 case.
quoted
quoted
+
+ fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
+ return fifo_size;
+}
+
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
+{
+ struct dwc3_ep *dep;
+ int fifo_depth;
+ int size;
+ int num;
+
+ if (!dwc->needs_fifo_resize)
+ return;
+
+ /* Read ep0IN related TXFIFO size */
+ dep = dwc->eps[1];
+ size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ if (DWC3_IP_IS(DWC31))
+ fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+ else
+ fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
The driver handles 3 IPs. Getting the fifo depth for DWC32 is the same
as DWC31. So the condition should be
if (DWC3_IP_IS(DWC3))
fifo_depth = ...
else
fifo_depth = ...
Understood.
quoted
quoted
+
+ dwc->last_fifo_depth = fifo_depth;
+ /* Clear existing TXFIFO for all IN eps except ep0 */
+ for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
+ num += 2) {
+ dep = dwc->eps[num];
+ /* Don't change TXFRAMNUM on usb31 version */
+ size = DWC3_IP_IS(DWC31) ?
+ dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
+ DWC31_GTXFIFOSIZ_TXFRAMNUM : 0;
+
Same here. Check for DWC32.
quoted
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
+ }
+ dwc->num_ep_resized = 0;
+}
+
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+ struct dwc3 *dwc = dep->dwc;
+ int fifo_0_start;
+ int ram1_depth;
+ int fifo_size;
+ int min_depth;
+ int num_in_ep;
+ int remaining;
+ int mult = 1;
+ int fifo;
+ int tmp;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
Maybe add a condition to check for Enhanced SuperSpeed only?
Since this logic applies for isoc endpoints as well in high speed mode,
for high bandwidth use cases, we can't limit it to SS only.
Ok. I was asking because you use 1024 as MPS in your calculation.
quoted
quoted
+
+ /* resize IN endpoints except ep0 */
+ if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+ return 0;
+
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+
+ if ((dep->endpoint.maxburst > 1 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
+ usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ mult = 3;
+
+ if (dep->endpoint.maxburst > 6 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
+ mult = 6;
You checked maxburst > 1 for isoc, but not when maxburst > 6. Why?
Also, "mult" is the term we usually use for isoc endpoints. Applying it
to bulk is confusing here.
Ok, let me rename it to something else that makes more sense. The isoc
endpoint check was targeted for mainly high-speed high bandwidth isoc
use cases, and I don't believe our results improved with a larger fifo
allocation, ie 6. (refer to below)
It should improve for isoc and reduce missed isoc error also. Most
applications only use 1-16KB max per interval, so you don't see the
impact as much.
quoted
How did we decide on 3 and 6? Are they arbitrary?
So actually in the databook, they have some recommendations for TXFIFO
sizes to use in "Table 4-3 Device Config Parameters." It mentions that
for burst capable endpoints to have a fifo size to fit at least 3
packets of maxpacket size.
There's also "Chapter 3 Cache, FIFO RAMs, and Bandwidth Requirements,"
which goes over a lot of optimizations that could be done based off your
system's overall latency. The sizes were chosen after we ran our peak
throughput and performance testing on our devices, and these values
netted the best throughput while also allowing enough fifo space for our
other USB endpoints. Also, there's going to be a limit on how much
improvement you see with respects to increasing the fifo size, since
your system will eventually be able to pull data out of the internal
fifo faster than it is being filled.
I added a patch a while back to check the max packet limit based on the
recommended minimum Rx/TxFIFO size
d94ea5319813 ("usb: dwc3: gadget: Properly set maxpacket limit")
The driver wouldn't match the endpoint if it doesn't meet the minimum
requirement of 3 MPS if the device is operating in SuperSpeed or
SuperSpeed Plus. Was the check for "3" necessary?
"6" is your tested value right? It may be different for different setup.
Can we pass this as a setting parameter from the devicetree property?
quoted
quoted
+
+ /* FIFO size for a single buffer */
+ fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
+
+ /* Calculate the number of remaining EPs w/o any FIFO */
+ num_in_ep = dwc->max_cfg_eps;
+ num_in_ep -= dwc->num_ep_resized;
+
+ /* Reserve at least one FIFO for the number of IN EPs */
+ min_depth = num_in_ep * (fifo + 1);
+ remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
Can "remaining" be a negative value? If so, I think it's clearer if you do
remaining = max_t(int, 0, remaining);
Sure.
quoted
quoted
+
+ /*
+ * We've already reserved 1 FIFO per EP, so check what we can fit in
+ * addition to it. If there is not enough remaining space, allocate
+ * all the remaining space to the EP.
+ */
+ fifo_size = (mult - 1) * fifo;
+ if (remaining < fifo_size) {
+ if (remaining > 0)
+ fifo_size = remaining;
+ else
+ fifo_size = 0;
Then use this condition instead:
if (remaining < fifo_size)
fifo_size = remaining;
quoted
+ }
+
+ fifo_size += fifo;
+ /* Last increment according to the TX FIFO size equation */
+ fifo_size++;
+
+ /* Check if TXFIFOs start at non-zero addr */
+ tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+ fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+ if (DWC3_IP_IS(DWC31))
+ dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+ else
+ dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
@@ -632,6 +787,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) int ret; if (!(dep->flags & DWC3_EP_ENABLED)) {+ ret = dwc3_gadget_resize_tx_fifos(dep);+ if (ret)+ return ret;+ ret = dwc3_gadget_start_config(dep); if (ret) return ret;
@@ -2485,6 +2645,39 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) return 0; }+static int dwc3_gadget_check_config(struct usb_gadget *g, unsigned long ep_map)
What's in ep_map? Can you document more to help with the review?
Yeah, I will add some more comments. Just to explain here briefly, this
check config callback is to address the concern pointed out by Felipe
where we could run out of txfifo memory while our USB composition is
being enabled. This would lead to an enumerated device, with
non-functioning endpoints.
The check config will be called during the function driver bind stage
(before we enumerate), and ep_map carries the number of endpoints (both
in and out) being used in a particular configuration. With this
information, the logic will ensure that there is enough txfifo space for
at least 1 fifo per endpoint. If not, we can catch the failure at the
composition bind stages. (although it would be odd to see a DWC3
controller with not enough txfifo ram for 1 fifo per ep) The point at
which we actually resize the fifo allocations, will always check to make
sure that there is enough fifo space for the remaining endpoints after
every resize.
Thanks
Wesley Cheng
Thanks for the info. I'll review more after you add more detail.
BR,
Thinh
quoted
Thanks,
Thinh
quoted
+{
+ struct dwc3 *dwc = gadget_to_dwc(g);
+ unsigned long in_ep_map;
+ int fifo_size = 0;
+ int ram1_depth;
+ int ep_num;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
+
+ /* Only interested in the IN endpoints */
+ in_ep_map = ep_map >> 16;
+ ep_num = hweight_long(in_ep_map);
+
+ if (ep_num <= dwc->max_cfg_eps)
+ return 0;
+
+ /* Update the max number of eps in the composition */
+ dwc->max_cfg_eps = ep_num;
+
+ fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
+ /* Based on the equation, increment by one for every ep */
+ fifo_size += dwc->max_cfg_eps;
+
+ /* Check if we can fit a single fifo per endpoint */
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+ if (fifo_size > ram1_depth)
+ return -ENOMEM;
+
+ return 0;
+}
+
static const struct usb_gadget_ops dwc3_gadget_ops = {
.get_frame = dwc3_gadget_get_frame,
.wakeup = dwc3_gadget_wakeup,
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
@@ -616,6 +616,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)return-EINVAL;caseUSB_STATE_ADDRESS:+dwc3_gadget_clear_tx_fifos(dwc);+ret=dwc3_ep0_delegate_req(dwc,ctrl);/* if the cfg matches and the cfg is non zero */if(cfg&&(!ret||(ret==USB_GADGET_DELAYED_STATUS))){
@@ -615,6 +615,161 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)staticvoiddwc3_stop_active_transfer(structdwc3_ep*dep,boolforce,boolinterrupt);+staticintdwc3_gadget_calc_tx_fifo_size(structdwc3*dwc,intmult)
Can you document what this function does?
Will do.
quoted
quoted
+{
+ int max_packet = 1024;
Maybe you can also document why you chose 1024 (e.g. applicable to
Enhanced SuperSpeed only?).
Sure. Its basically applicable for SS and isoc (hs/ss) use cases since
max packet size is 1024 in both cases.
Highspeed bulk MPS is 512. Fullspeed varies more (bulk max MPS is 64 and
isoc is 1023).
However, we can keep it simple with 1024 as if it's ok to over estimate.
Just need to note that here.
quoted
quoted
quoted
+ int fifo_size;
+ int mdwidth;
+
+ mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* MDWIDTH is represented in bits, we need it in bytes */
+ mdwidth >>= 3;
mdwidth for DWC32 requires to read hwparams6 for the upper 2 significant
bits. Can we add a check for DWC32 also? You can check how we're doing
it now in the current code.
Sure. I'll make sure to get the correct registers for the DWC32 case.
quoted
quoted
+
+ fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
+ return fifo_size;
+}
+
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
+{
+ struct dwc3_ep *dep;
+ int fifo_depth;
+ int size;
+ int num;
+
+ if (!dwc->needs_fifo_resize)
+ return;
+
+ /* Read ep0IN related TXFIFO size */
+ dep = dwc->eps[1];
+ size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ if (DWC3_IP_IS(DWC31))
+ fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+ else
+ fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
The driver handles 3 IPs. Getting the fifo depth for DWC32 is the same
as DWC31. So the condition should be
if (DWC3_IP_IS(DWC3))
fifo_depth = ...
else
fifo_depth = ...
Understood.
quoted
quoted
+
+ dwc->last_fifo_depth = fifo_depth;
+ /* Clear existing TXFIFO for all IN eps except ep0 */
+ for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
+ num += 2) {
+ dep = dwc->eps[num];
+ /* Don't change TXFRAMNUM on usb31 version */
+ size = DWC3_IP_IS(DWC31) ?
+ dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
+ DWC31_GTXFIFOSIZ_TXFRAMNUM : 0;
+
Same here. Check for DWC32.
quoted
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
+ }
+ dwc->num_ep_resized = 0;
+}
+
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+ struct dwc3 *dwc = dep->dwc;
+ int fifo_0_start;
+ int ram1_depth;
+ int fifo_size;
+ int min_depth;
+ int num_in_ep;
+ int remaining;
+ int mult = 1;
+ int fifo;
+ int tmp;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
Maybe add a condition to check for Enhanced SuperSpeed only?
Since this logic applies for isoc endpoints as well in high speed mode,
for high bandwidth use cases, we can't limit it to SS only.
Ok. I was asking because you use 1024 as MPS in your calculation.
quoted
quoted
quoted
+
+ /* resize IN endpoints except ep0 */
+ if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+ return 0;
+
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+
+ if ((dep->endpoint.maxburst > 1 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
+ usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ mult = 3;
+
+ if (dep->endpoint.maxburst > 6 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
+ mult = 6;
You checked maxburst > 1 for isoc, but not when maxburst > 6. Why?
Also, "mult" is the term we usually use for isoc endpoints. Applying it
to bulk is confusing here.
Ok, let me rename it to something else that makes more sense. The isoc
endpoint check was targeted for mainly high-speed high bandwidth isoc
use cases, and I don't believe our results improved with a larger fifo
allocation, ie 6. (refer to below)
It should improve for isoc and reduce missed isoc error also. Most
applications only use 1-16KB max per interval, so you don't see the
impact as much.
quoted
quoted
How did we decide on 3 and 6? Are they arbitrary?
So actually in the databook, they have some recommendations for TXFIFO
sizes to use in "Table 4-3 Device Config Parameters." It mentions that
for burst capable endpoints to have a fifo size to fit at least 3
packets of maxpacket size.
There's also "Chapter 3 Cache, FIFO RAMs, and Bandwidth Requirements,"
which goes over a lot of optimizations that could be done based off your
system's overall latency. The sizes were chosen after we ran our peak
throughput and performance testing on our devices, and these values
netted the best throughput while also allowing enough fifo space for our
other USB endpoints. Also, there's going to be a limit on how much
improvement you see with respects to increasing the fifo size, since
your system will eventually be able to pull data out of the internal
fifo faster than it is being filled.
I added a patch a while back to check the max packet limit based on the
recommended minimum Rx/TxFIFO size
d94ea5319813 ("usb: dwc3: gadget: Properly set maxpacket limit")
The driver wouldn't match the endpoint if it doesn't meet the minimum
requirement of 3 MPS if the device is operating in SuperSpeed or
SuperSpeed Plus. Was the check for "3" necessary?
Hi Thinh,
Please correct me if I'm wrong, but when a function driver requests for
an endpoint using usb_ep_autoconfig(), most of the time it passes in a
FS descriptor that doesn't have the wMaxPacketSize parameter set (0),
which means it will probably fetch the first unused endpoint. (at least
this is what I noticed for the BULK ep cases)
In this case, it would be hard to determine if the endpoint selected
would already have the constraint you added factored in.
"6" is your tested value right? It may be different for different setup.
Can we pass this as a setting parameter from the devicetree property?
Definitely can agree to that. We can make things a bit more flexible
depending on the system. Maybe create a new property, and default it to
6 if "do_fifo_resize" is set, but this parameter is not defined.
Thanks
Wesley Cheng
quoted
quoted
quoted
+
+ /* FIFO size for a single buffer */
+ fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
+
+ /* Calculate the number of remaining EPs w/o any FIFO */
+ num_in_ep = dwc->max_cfg_eps;
+ num_in_ep -= dwc->num_ep_resized;
+
+ /* Reserve at least one FIFO for the number of IN EPs */
+ min_depth = num_in_ep * (fifo + 1);
+ remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
Can "remaining" be a negative value? If so, I think it's clearer if you do
remaining = max_t(int, 0, remaining);
Sure.
quoted
quoted
+
+ /*
+ * We've already reserved 1 FIFO per EP, so check what we can fit in
+ * addition to it. If there is not enough remaining space, allocate
+ * all the remaining space to the EP.
+ */
+ fifo_size = (mult - 1) * fifo;
+ if (remaining < fifo_size) {
+ if (remaining > 0)
+ fifo_size = remaining;
+ else
+ fifo_size = 0;
Then use this condition instead:
if (remaining < fifo_size)
fifo_size = remaining;
quoted
+ }
+
+ fifo_size += fifo;
+ /* Last increment according to the TX FIFO size equation */
+ fifo_size++;
+
+ /* Check if TXFIFOs start at non-zero addr */
+ tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+ fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+ if (DWC3_IP_IS(DWC31))
+ dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+ else
+ dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
@@ -632,6 +787,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) int ret; if (!(dep->flags & DWC3_EP_ENABLED)) {+ ret = dwc3_gadget_resize_tx_fifos(dep);+ if (ret)+ return ret;+ ret = dwc3_gadget_start_config(dep); if (ret) return ret;
@@ -2485,6 +2645,39 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) return 0; }+static int dwc3_gadget_check_config(struct usb_gadget *g, unsigned long ep_map)
What's in ep_map? Can you document more to help with the review?
Yeah, I will add some more comments. Just to explain here briefly, this
check config callback is to address the concern pointed out by Felipe
where we could run out of txfifo memory while our USB composition is
being enabled. This would lead to an enumerated device, with
non-functioning endpoints.
The check config will be called during the function driver bind stage
(before we enumerate), and ep_map carries the number of endpoints (both
in and out) being used in a particular configuration. With this
information, the logic will ensure that there is enough txfifo space for
at least 1 fifo per endpoint. If not, we can catch the failure at the
composition bind stages. (although it would be odd to see a DWC3
controller with not enough txfifo ram for 1 fifo per ep) The point at
which we actually resize the fifo allocations, will always check to make
sure that there is enough fifo space for the remaining endpoints after
every resize.
Thanks
Wesley Cheng
Thanks for the info. I'll review more after you add more detail.
BR,
Thinh
quoted
quoted
Thanks,
Thinh
quoted
+{
+ struct dwc3 *dwc = gadget_to_dwc(g);
+ unsigned long in_ep_map;
+ int fifo_size = 0;
+ int ram1_depth;
+ int ep_num;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
+
+ /* Only interested in the IN endpoints */
+ in_ep_map = ep_map >> 16;
+ ep_num = hweight_long(in_ep_map);
+
+ if (ep_num <= dwc->max_cfg_eps)
+ return 0;
+
+ /* Update the max number of eps in the composition */
+ dwc->max_cfg_eps = ep_num;
+
+ fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
+ /* Based on the equation, increment by one for every ep */
+ fifo_size += dwc->max_cfg_eps;
+
+ /* Check if we can fit a single fifo per endpoint */
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+ if (fifo_size > ram1_depth)
+ return -ENOMEM;
+
+ return 0;
+}
+
static const struct usb_gadget_ops dwc3_gadget_ops = {
.get_frame = dwc3_gadget_get_frame,
.wakeup = dwc3_gadget_wakeup,
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.
Signed-off-by: Wesley Cheng <redacted>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 2 +
drivers/usb/dwc3/gadget.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 206 insertions(+)
@@ -616,6 +616,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)return-EINVAL;caseUSB_STATE_ADDRESS:+dwc3_gadget_clear_tx_fifos(dwc);+ret=dwc3_ep0_delegate_req(dwc,ctrl);/* if the cfg matches and the cfg is non zero */if(cfg&&(!ret||(ret==USB_GADGET_DELAYED_STATUS))){
@@ -615,6 +615,161 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)staticvoiddwc3_stop_active_transfer(structdwc3_ep*dep,boolforce,boolinterrupt);+staticintdwc3_gadget_calc_tx_fifo_size(structdwc3*dwc,intmult)
Can you document what this function does?
Will do.
quoted
quoted
+{
+ int max_packet = 1024;
Maybe you can also document why you chose 1024 (e.g. applicable to
Enhanced SuperSpeed only?).
Sure. Its basically applicable for SS and isoc (hs/ss) use cases since
max packet size is 1024 in both cases.
Highspeed bulk MPS is 512. Fullspeed varies more (bulk max MPS is 64 and
isoc is 1023).
However, we can keep it simple with 1024 as if it's ok to over estimate.
Just need to note that here.
quoted
quoted
quoted
+ int fifo_size;
+ int mdwidth;
+
+ mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* MDWIDTH is represented in bits, we need it in bytes */
+ mdwidth >>= 3;
mdwidth for DWC32 requires to read hwparams6 for the upper 2 significant
bits. Can we add a check for DWC32 also? You can check how we're doing
it now in the current code.
Sure. I'll make sure to get the correct registers for the DWC32 case.
quoted
quoted
+
+ fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
+ return fifo_size;
+}
+
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
+{
+ struct dwc3_ep *dep;
+ int fifo_depth;
+ int size;
+ int num;
+
+ if (!dwc->needs_fifo_resize)
+ return;
+
+ /* Read ep0IN related TXFIFO size */
+ dep = dwc->eps[1];
+ size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ if (DWC3_IP_IS(DWC31))
+ fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+ else
+ fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
The driver handles 3 IPs. Getting the fifo depth for DWC32 is the same
as DWC31. So the condition should be
if (DWC3_IP_IS(DWC3))
fifo_depth = ...
else
fifo_depth = ...
Understood.
quoted
quoted
+
+ dwc->last_fifo_depth = fifo_depth;
+ /* Clear existing TXFIFO for all IN eps except ep0 */
+ for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
+ num += 2) {
+ dep = dwc->eps[num];
+ /* Don't change TXFRAMNUM on usb31 version */
+ size = DWC3_IP_IS(DWC31) ?
+ dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
+ DWC31_GTXFIFOSIZ_TXFRAMNUM : 0;
+
Same here. Check for DWC32.
quoted
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
+ }
+ dwc->num_ep_resized = 0;
+}
+
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+ struct dwc3 *dwc = dep->dwc;
+ int fifo_0_start;
+ int ram1_depth;
+ int fifo_size;
+ int min_depth;
+ int num_in_ep;
+ int remaining;
+ int mult = 1;
+ int fifo;
+ int tmp;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
Maybe add a condition to check for Enhanced SuperSpeed only?
Since this logic applies for isoc endpoints as well in high speed mode,
for high bandwidth use cases, we can't limit it to SS only.
Ok. I was asking because you use 1024 as MPS in your calculation.
quoted
quoted
quoted
+
+ /* resize IN endpoints except ep0 */
+ if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+ return 0;
+
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+
+ if ((dep->endpoint.maxburst > 1 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
+ usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ mult = 3;
+
+ if (dep->endpoint.maxburst > 6 &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
+ mult = 6;
You checked maxburst > 1 for isoc, but not when maxburst > 6. Why?
Also, "mult" is the term we usually use for isoc endpoints. Applying it
to bulk is confusing here.
Ok, let me rename it to something else that makes more sense. The isoc
endpoint check was targeted for mainly high-speed high bandwidth isoc
use cases, and I don't believe our results improved with a larger fifo
allocation, ie 6. (refer to below)
It should improve for isoc and reduce missed isoc error also. Most
applications only use 1-16KB max per interval, so you don't see the
impact as much.
quoted
quoted
How did we decide on 3 and 6? Are they arbitrary?
So actually in the databook, they have some recommendations for TXFIFO
sizes to use in "Table 4-3 Device Config Parameters." It mentions that
for burst capable endpoints to have a fifo size to fit at least 3
packets of maxpacket size.
There's also "Chapter 3 Cache, FIFO RAMs, and Bandwidth Requirements,"
which goes over a lot of optimizations that could be done based off your
system's overall latency. The sizes were chosen after we ran our peak
throughput and performance testing on our devices, and these values
netted the best throughput while also allowing enough fifo space for our
other USB endpoints. Also, there's going to be a limit on how much
improvement you see with respects to increasing the fifo size, since
your system will eventually be able to pull data out of the internal
fifo faster than it is being filled.
I added a patch a while back to check the max packet limit based on the
recommended minimum Rx/TxFIFO size
d94ea5319813 ("usb: dwc3: gadget: Properly set maxpacket limit")
The driver wouldn't match the endpoint if it doesn't meet the minimum
requirement of 3 MPS if the device is operating in SuperSpeed or
SuperSpeed Plus. Was the check for "3" necessary?
Hi Thinh,
Please correct me if I'm wrong, but when a function driver requests for
an endpoint using usb_ep_autoconfig(), most of the time it passes in a
FS descriptor that doesn't have the wMaxPacketSize parameter set (0),
which means it will probably fetch the first unused endpoint. (at least
this is what I noticed for the BULK ep cases)
In this case, it would be hard to determine if the endpoint selected
would already have the constraint you added factored in.
The gadget driver should pass in the descriptor that matches the
selected gadget_driver->max_speed or maximum HW speed capability to
usb_ep_autoconfig*() . Otherwise, the usb_ep_autoconfig*() doesn't match
the right endpoint for the selected speed. This is something that needs
to be fixed. I'm not sure how it will impact some existing setup though.
As you said, most of the gadget drivers ignore matching wMaxPacketSize
(and others parameters) previously. IMO, this should be fixed regardless.
Thanks,
Thinh
quoted
"6" is your tested value right? It may be different for different setup.
Can we pass this as a setting parameter from the devicetree property?
Definitely can agree to that. We can make things a bit more flexible
depending on the system. Maybe create a new property, and default it to
6 if "do_fifo_resize" is set, but this parameter is not defined.
Thanks
Wesley Cheng
quoted
quoted
quoted
quoted
+
+ /* FIFO size for a single buffer */
+ fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
+
+ /* Calculate the number of remaining EPs w/o any FIFO */
+ num_in_ep = dwc->max_cfg_eps;
+ num_in_ep -= dwc->num_ep_resized;
+
+ /* Reserve at least one FIFO for the number of IN EPs */
+ min_depth = num_in_ep * (fifo + 1);
+ remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
Can "remaining" be a negative value? If so, I think it's clearer if you do
remaining = max_t(int, 0, remaining);
Sure.
quoted
quoted
+
+ /*
+ * We've already reserved 1 FIFO per EP, so check what we can fit in
+ * addition to it. If there is not enough remaining space, allocate
+ * all the remaining space to the EP.
+ */
+ fifo_size = (mult - 1) * fifo;
+ if (remaining < fifo_size) {
+ if (remaining > 0)
+ fifo_size = remaining;
+ else
+ fifo_size = 0;
Then use this condition instead:
if (remaining < fifo_size)
fifo_size = remaining;
quoted
+ }
+
+ fifo_size += fifo;
+ /* Last increment according to the TX FIFO size equation */
+ fifo_size++;
+
+ /* Check if TXFIFOs start at non-zero addr */
+ tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+ fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+ if (DWC3_IP_IS(DWC31))
+ dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+ else
+ dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
@@ -632,6 +787,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) int ret; if (!(dep->flags & DWC3_EP_ENABLED)) {+ ret = dwc3_gadget_resize_tx_fifos(dep);+ if (ret)+ return ret;+ ret = dwc3_gadget_start_config(dep); if (ret) return ret;
@@ -2485,6 +2645,39 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) return 0; }+static int dwc3_gadget_check_config(struct usb_gadget *g, unsigned long ep_map)
What's in ep_map? Can you document more to help with the review?
Yeah, I will add some more comments. Just to explain here briefly, this
check config callback is to address the concern pointed out by Felipe
where we could run out of txfifo memory while our USB composition is
being enabled. This would lead to an enumerated device, with
non-functioning endpoints.
The check config will be called during the function driver bind stage
(before we enumerate), and ep_map carries the number of endpoints (both
in and out) being used in a particular configuration. With this
information, the logic will ensure that there is enough txfifo space for
at least 1 fifo per endpoint. If not, we can catch the failure at the
composition bind stages. (although it would be odd to see a DWC3
controller with not enough txfifo ram for 1 fifo per ep) The point at
which we actually resize the fifo allocations, will always check to make
sure that there is enough fifo space for the remaining endpoints after
every resize.
Thanks
Wesley Cheng
Thanks for the info. I'll review more after you add more detail.
BR,
Thinh
quoted
quoted
Thanks,
Thinh
quoted
+{
+ struct dwc3 *dwc = gadget_to_dwc(g);
+ unsigned long in_ep_map;
+ int fifo_size = 0;
+ int ram1_depth;
+ int ep_num;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
+
+ /* Only interested in the IN endpoints */
+ in_ep_map = ep_map >> 16;
+ ep_num = hweight_long(in_ep_map);
+
+ if (ep_num <= dwc->max_cfg_eps)
+ return 0;
+
+ /* Update the max number of eps in the composition */
+ dwc->max_cfg_eps = ep_num;
+
+ fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
+ /* Based on the equation, increment by one for every ep */
+ fifo_size += dwc->max_cfg_eps;
+
+ /* Check if we can fit a single fifo per endpoint */
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+ if (fifo_size > ram1_depth)
+ return -ENOMEM;
+
+ return 0;
+}
+
static const struct usb_gadget_ops dwc3_gadget_ops = {
.get_frame = dwc3_gadget_get_frame,
.wakeup = dwc3_gadget_wakeup,