Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init
From: Thierry Reding <hidden>
Date: 2021-01-19 23:35:51
Also in:
linux-clk, linux-tegra, linux-usb, lkml
On Tue, Jan 19, 2021 at 04:55:33PM +0800, JC Kuo wrote:
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Thierry Reding <redacted> --- v6: no change v5: no change v4: no change v3: no change drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-)
Michael, Stephen, here's patch 2 of the hardware sequencer series that would need an Acked-by so that it can go through a different tree. Thanks, Thierry
quoted hunk ↗ jump to hunk
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c@@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - val = pll_readl_misc(pll); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val = pll_readl(pll->params->aux_reg, pll); - val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags);-- 2.25.1
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