RE: [PATCH] dt-bindings: mips: lantiq: Document Lantiq Xway DMA bindings
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: 2021-01-16 20:46:26
Also in:
linux-mips, lkml
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: 2021-01-16 20:46:26
Also in:
linux-mips, lkml
(another late reply from me, sorry)
+required: + - compatible + - reg
This is actually an older IP variant of what can be found in the Intel LGM SoCs. The dt-bindings are currently being upstreamed for that newer SoC in [0]. Based on "DOs and DON’Ts for designing and writing Devicetree bindings" I think some more mandatory properties are needed, even though our driver currently uses none of them: - interrupts: as far as I know the IP on the Lantiq SoCs has (at least) one interrupt for each DMA channel. That means: 28 interrupts on the xRX200 SoCs - I *assume* (but I have not researched if that's really the case) that the Lantiq variant also has at least one clock input and a reset line - since we don't have a proper DMA driver yet I can't comment what we should use for #dma-cells
+examples:
+ - |
+ dma@e104100 {note to self: it seems that both dma@ and dma-controller@ are used in existing schemas (the latter having twice as many occurrences though): $ grep -R dma@ Documentation/devicetree/bindings/dma/* | wc -l 20 $ grep -R dma-controller@ Documentation/devicetree/bindings/dma/* | wc -l 45 Best regards, Martin [0] https://patchwork.ozlabs.org/project/devicetree-bindings/patch/0864b9bfa6e2b8b5e7ad9a7a739ca3274f66493c.1610703653.git.mallikarjunax.reddy@linux.intel.com/ [1] https://www.kernel.org/doc/html/latest/devicetree/bindings/writing-bindings.html