Re: [PATCH 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings

Hi Philipp,


On Thu, 2021-01-14 at 10:39 +0100, Philipp Zabel wrote:

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Hi Steen,

On Wed, 2021-01-13 at 21:19 +0100, Steen Hegelund wrote:

quoted

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
 .../bindings/reset/microchip,rst.yaml         | 52
+++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/reset/microchip,rst.yaml

diff --git
a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index 000000000000..b5526753e85d

--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+  - Steen Hegelund <steen.hegelund@microchip.com>
+  - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+  The Microchip Sparx5 Switch provides reset control and

implements the following
+  functions
+    - One Time Switch Core Reset (Soft Reset)
+
+properties:
+  $nodename:
+    pattern: "^reset-controller@[0-9a-f]+$"
+
+  compatible:
+    const: microchip,sparx5-switch-reset
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+  syscons:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    description: Array of syscons used to access reset registers
+    minItems: 2

The order seems to be important in the driver, so this should specify
which is the CPU syscon and which is the GCB syscon. I'm not sure if
it
would be better to have two separately named syscon properties with a
single phandle each.

Yes you got a point.  I will change that.

regards
Philipp

BR
Steen