Hi Wolfram,

On Sun, Dec 27, 2020 at 2:06 PM Wolfram Sang
[off-list ref] wrote:

Document the compatible value for the RAVB block in the Renesas R-Car
V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need
to add the new compatible.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

EtherAVB on R-Car V3U does have the Tx clock internal Delay Mode
bit in the APSR register, so its compatible value should be added to
the list of SoCs where tx-internal-delay-ps is required.

With that fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

The various Counter Registers starting at offset 0x700 are limited to
16-bit values, like on R-Car Gen2, while they support 32-bit values on
other R-Car Gen3 variants. The driver uses only the Transmit Retry Over
Counter Register (TROCR), for statistics, so we can just ignore that
difference.

V3U also has a new block of registers related to UDP/IP support (offset
0x800 and up).  I guess we can just ignore them too, for now.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds