Re: [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC
From: Aurelien Jarno <aurelien@aurel32.net>
Date: 2020-12-26 01:18:15
Also in:
linux-riscv, lkml
On 2020-12-04 00:58, Atish Patra wrote:
quoted hunk ↗ jump to hunk
Enable Microchip PolarFire ICICLE soc config in defconfig. It allows the default upstream kernel to boot on PolarFire ICICLE board. Signed-off-by: Atish Patra <redacted> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <redacted> --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+)diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d222d353d86d..2660fa05451e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig@@ -16,6 +16,7 @@ CONFIG_EXPERT=y CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SMP=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y@@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y +CONFIG_SDHCI=y
I guess this should be CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC=y CONFIG_MMC_SPI=y CONFIG_RTC_CLASS=y
Regards, Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net