RE: [PATCH v3 2/2] phy: intel: Add Keem Bay USB PHY support

Hi Andy.

-----Original Message-----
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Sent: Thursday, November 12, 2020 10:29 PM
To: Wan Mohamad, Wan Ahmad Zainie
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Cc: kishon@ti.com; vkoul@kernel.org; robh+dt@kernel.org; linux-
kernel@vger.kernel.org; devicetree@vger.kernel.org;
mgross@linux.intel.com; Raja Subramanian, Lakshmi Bai
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Subject: Re: [PATCH v3 2/2] phy: intel: Add Keem Bay USB PHY support

On Thu, Nov 12, 2020 at 05:58:21PM +0800, Wan Ahmad Zainie wrote:

quoted

Add support for USB PHY on Intel Keem Bay SoC.

Any elaboration here? What is this PHY (USB2 or USB3 or?.. etc)?

Yes, I can elaborate this.

...

quoted

+config PHY_INTEL_KEEMBAY_USB
+	tristate "Intel Keem Bay USB PHY driver"

quoted

+	depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)

It seems other drivers that are not using ARM specific calls moved to

	depends on ARCH_KEEMBAY || COMPILE_TEST

I will fix in v4.

quoted

+	depends on HAS_IOMEM
+	select GENERIC_PHY
+	select REGMAP_MMIO

...

quoted

+#define USS_CPR_MASK		0x7f

GENMASK() ?

I will fix in v4.

...

quoted

+static const struct regmap_config keembay_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,

.max_register?

It is optional. But yes, I can add,
.max_register = USS_USB_TIEOFFS_CONSTANTS_REG1

quoted

+};

--
With Best Regards,
Andy Shevchenko

Best regards,
Zainie