Thread (6 messages) 6 messages, 2 authors, 2020-09-11

Re: [RESEND PATCH v12 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC

From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: 2020-09-07 15:06:12
Also in: linux-mips, lkml

Miquel Raynal [off-list ref] wrote on Mon, 7 Sep 2020
15:20:25 +0200:
Hi Murugan,

A few more comments below, but I guess the driver looks better now.
quoted
+struct ebu_nand_controller {
+	struct nand_controller controller;
+	struct nand_chip chip;
+	struct device *dev;
+	void __iomem *ebu;
+	void __iomem *hsnand;
+	struct dma_chan *dma_tx;
+	struct dma_chan *dma_rx;
+	struct completion dma_access_complete;
+	unsigned long clk_rate;
+	struct clk *clk;
+	u32 nd_para0;
+	u8 cs_num;
+	struct ebu_nand_cs cs[MAX_CS];
+};
+
+static inline struct ebu_nand_controller *nand_to_ebu(struct nand_chip *chip)
+{
+	return container_of(chip, struct ebu_nand_controller, chip);
+}
+
+static u8 ebu_nand_readb(struct nand_chip *chip)  
Can't you prefix with intel_ instead of ebu_ ?
Actually not, as the IP is shared with MIPS IIUC, just ignore this
comment.

Thanks,
Miquèl
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