Re: [PATCH 2/7] spi: fsi: Fix clock running too fast

On Thu, 20 Aug 2020 at 21:06, Eddie James [off-list ref] wrote:

On 8/20/20 12:12 PM, Mark Brown wrote:

quoted

On Thu, Aug 20, 2020 at 12:02:23PM -0500, Eddie James wrote:

quoted

From: Brad Bishop <redacted>

Use a clock divider tuned to a 200MHz FSI clock.  Use of the previous
divider at 200MHz results in corrupt data from endpoint devices. Ideally
the clock divider would be calculated from the FSI clock, but that
would require some significant work on the FSI driver.

Presumably this divider was chosen for FSI clocks that aren't 200MHz -
how will those be handled?

They aren't handled at the moment, but 200MHz FSI represents the worst
case, as it's the maximum. Slower FSI clocks will simply result in
slower SPI clocks.

That would be a good addition to the commit message, as I had the same
question too.

Cheers,

Joel