Re: [PATCH v3 43/44] dt: document HiSilicon SPMI controller and mfd/regulator properties

On Tue, Aug 18, 2020 at 4:18 PM Mauro Carvalho Chehab
[off-list ref] wrote:

Em Tue, 18 Aug 2020 11:07:55 -0600
Rob Herring [off-list ref] escreveu:

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+  spmi-channel:
+    description: number of the SPMI channel where the PMIC is connected

This looks like a common (to SPMI), but it's not something defined in
spmi.txt

This one is not part of the SPMI core. It is stored inside a private
structure inside at the HiSilicon spmi controller driver. It is stored
there as ctrl_dev->channel, and it is used to calculate the register offset
for readl():

    offset  = SPMI_APB_SPMI_STATUS_BASE_ADDR;
    offset += SPMI_CHANNEL_OFFSET * ctrl_dev->channel + SPMI_SLAVE_OFFSET * sid;
    do {
            status = readl(base + offset);
    ...

The SPMI bus is somewhat similar to I2C: it is a 2-wire serial bus
with up to 16 devices connected to it.

Now, most modern I2C chipsets provide multiple independent I2C
channels, on different pins. Also, on some chipsets, certain
GPIO pins can be used either as GPIO or as I2C.

I strongly suspect that this is the case here: according with
the Hikey 970 schematics:

    https://www.96boards.org/documentation/consumer/hikey/hikey970/hardware-docs/files/hikey970-schematics.pdf

The pins used by SPMI clock/data can also be used as GPIO.

While I don't have access to the datasheets for Kirin 970 (or any other
chipsets on this board), for me, it sounds that different GPIO pins
are allowed to use SPMI. The "spmi-channel" property specifies
what pins will be used for SPMI, among the ones that are
compatible with MIPI SPMI specs.

Based on this, I think it should be called 'hisilicon,spmi-channel' as
it is vendor specific.

I'm fine with "hisilicon,spmi-channel".

Humm, QCom has a 'qcom,channel' property for SPMI. Seems like maybe it
should be a common thing.

Rob