Re: [PATCHv2] arm64: dts: qcom: sc7180: Fix the LLCC base register size

Hi,


On Tue, Aug 18, 2020 at 7:55 AM Sai Prakash Ranjan
[off-list ref] wrote:

There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.

Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan <redacted>
---

Changes in v2:
 * Edit commit msg to remove confusing references (Doug).

---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

I can't validate against any datasheets, but it does what it says and
seems sane.

Reviewed-by: Douglas Anderson <dianders@chromium.org>