ipq8074 has two pcie ports, one gen2 and one gen3 ports. with phy
support already available for gen2 pcie ports add support for pcie gen3
port phy.

Co-developed-by: Selvam Sathappan Periakaruppan <redacted>
Signed-off-by: Selvam Sathappan Periakaruppan <redacted>
Signed-off-by: Sivaprakash Murugesan <redacted>
---
 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 137 ++++++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.c       | 172 +++++++++++++++++++++++++++++-
 2 files changed, 307 insertions(+), 2 deletions(-)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h

diff --git a/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
new file mode 100644
index 000000000000..bb567673d9b5
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h

@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0*

@@ -2550,8 +2707,16 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
 
 	init.ops = &clk_fixed_rate_ops;
 
-	/* controllers using QMP phys use 125MHz pipe clock interface */
-	fixed->fixed_rate = 125000000;
+	/*
+	 * controllers using QMP phys use 125MHz pipe clock interface unless
+	 * other frequency is specified in dts
+	 */
+	ret = of_property_read_u32(np, "clock-output-rate",
+				   (u32 *)&fixed->fixed_rate);