Re: [RFC PATCH 1/6] dt-bindings: display/bridge: Add binding for input mux bridge

Hi Rob,
On Thu, May 28, 2020 at 01:48:04PM -0600, Rob Herring wrote:

On Fri, May 15, 2020 at 03:12:10PM +0200, Guido Günther wrote:

quoted

The bridge allows to select the input source via a mux controller.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
---
 .../display/bridge/mux-input-bridge.yaml      | 123 ++++++++++++++++++
 1 file changed, 123 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml
new file mode 100644
index 000000000000..4029cf63ee5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/mux-input-bridge.yaml

@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/mux-input-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DRM input source selection via multiplexer

DRM is not a hardware thing.

I thought about naming the mux pixel-input-mux (input-mux sounding too
generic) but then i hit rockchip-drm and went for that name.  The
binding itself is not a drm thing in itself it really aims to model how
the mux is placed in the 'display pipeline' of the SoC (as Laurent
explained). Should I go with pixel-input-mux?

The graph binding is already designed to support muxing. Generally, 
multiple endpoints on an input node is a mux. So either the device with 
the input ports knows how to select the input, or you just need a 
mux-control property for the port to have some other device implement 
the control.

A mux control property is how it's modeled at the moment but that is
very SoC specific.

You could do it like you have below. That would be appropriate if 
there's a separate h/w device controlling the muxing. Say for example 
some board level device controlled by i2c.

It's a different part of the SoC that lives in a register range very
separate (iomuxc_gpr) from MIPI/DSI (nwl). Does that qualify?

Cheers,
 -- Guido

Rob