[PATCH v2 5/6] clocksource: mips-gic-timer: Register as sched_clock
From: <hidden>
Date: 2020-03-24 17:45:06
Also in:
lkml
Subsystem:
clocksource, clockevent drivers, mips core drivers, the rest · Maintainers:
Daniel Lezcano, Thomas Gleixner, Thomas Bogendoerfer, Linus Torvalds
From: Paul Burton <paulburton@kernel.org> The MIPS GIC timer is well suited for use as sched_clock, so register it as such. Whilst the existing gic_read_count() function matches the prototype needed by sched_clock_register() already, we split it into 2 functions in order to remove the need to evaluate the mips_cm_is64 condition within each call since sched_clock should be as fast as possible. Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Serge Semin <redacted> Cc: Alexey Malahov <redacted> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Ralf Baechle <redacted> Cc: Thomas Gleixner <redacted> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Andy Shevchenko <redacted> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org --- drivers/clocksource/mips-gic-timer.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 37671a5d4ed9..8239ff99cfe4 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c@@ -16,6 +16,7 @@ #include <linux/notifier.h> #include <linux/of_irq.h> #include <linux/percpu.h> +#include <linux/sched_clock.h> #include <linux/smp.h> #include <linux/time.h> #include <asm/mips-cps.h>
@@ -24,13 +25,10 @@ static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); static int gic_timer_irq; static unsigned int gic_frequency; -static u64 notrace gic_read_count(void) +static u64 notrace gic_read_count_2x32(void) { unsigned int hi, hi2, lo; - if (mips_cm_is64) - return read_gic_counter(); - do { hi = read_gic_counter_32h(); lo = read_gic_counter_32l();
@@ -40,6 +38,19 @@ static u64 notrace gic_read_count(void) return (((u64) hi) << 32) + lo; } +static u64 notrace gic_read_count_64(void) +{ + return read_gic_counter(); +} + +static u64 notrace gic_read_count(void) +{ + if (mips_cm_is64) + return gic_read_count_64(); + + return gic_read_count_2x32(); +} + static int gic_next_event(unsigned long delta, struct clock_event_device *evt) { int cpu = cpumask_first(evt->cpumask);
@@ -228,6 +239,10 @@ static int __init gic_clocksource_of_init(struct device_node *node) /* And finally start the counter */ clear_gic_config(GIC_CONFIG_COUNTSTOP); + sched_clock_register(mips_cm_is64 ? + gic_read_count_64 : gic_read_count_2x32, + 64, gic_frequency); + return 0; } TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
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2.25.1