[PATCH 3/6] dt-bindings: Add Baikal-T1 L2-cache Control Block dts bindings file
From: <hidden>
Date: 2020-03-06 13:07:39
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lkml
Subsystem:
open firmware and flattened device tree bindings, the rest · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
From: Serge Semin <redacted> There is a single register provided by the SoC system controller, which can be used to tune the L2-cache up. It only provides a way to change the L2-RAM access latencies. So aside from the MMIO region with that setting and "be,bt1-l2-ctl" compatible string the device node can be optionally equipped with the properties of Tag/Data/WS latencies. Signed-off-by: Serge Semin <redacted> Signed-off-by: Alexey Malahov <redacted> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <redacted> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <redacted> Cc: soc@kernel.org --- .../bindings/soc/baikal-t1/be,bt1-l2-ctl.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-l2-ctl.yaml
diff --git a/Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-l2-ctl.yaml
new file mode 100644
index 000000000000..8769b3fa517c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-l2-ctl.yaml@@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +# +# Baikal-T1 L2-cache Control Block Device Tree Bindings. +# +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/baikal-t1/be,bt1-l2-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 L2-cache Control Block + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: | + Baikal-T1 exposes a few settings to tune the MIPS P5600 CM2 L2-cache + performance up. In particular it's possible to change the Tag, Data and + Way-select RAM access latencies. This bindings file describes the system + controller block, which provides an interface to set the tuning up. + +allOf: + - if: + properties: + compatible: + contains: + const: syscon + then: + $ref: ../../mfd/syscon.yaml# + else: + properties: + reg-io-width: false + + little-endian: false + +properties: + compatible: + oneOf: + - description: P5600 CM2 L2-cache RAM external configuration block. + const: be,bt1-l2-ctl + - description: P5600 CM2 L2-cache RAM system controller block. + items: + - const: be,bt1-l2-ctl + - const: syscon + + reg: + description: MMIO register with MIPS P5600 CM2 L2-cache RAM settings. + maxItems: 1 + + be,l2-ws-latency: + description: Cycles of latency for Way-select RAM accesses. + default: 0 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 3 + + be,l2-tag-latency: + description: Cycles of latency for Tag RAM accesses. + default: 0 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 3 + + be,l2-data-latency: + description: Cycles of latency for Data RAM accesses. + default: 1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 3 + + reg-io-width: + const: 4 + + little-endian: true + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + l2_ctl1: l2@1F04D028 { + compatible = "be,bt1-l2-ctl"; + reg = <0x1F04D028 0x004>; + + be,l2-ws-latency = <0>; + be,l2-tag-latency = <0>; + be,l2-data-latency = <1>; + }; + - | + l2_ctl2: l2@1F04D028 { + compatible = "be,bt1-l2-ctl", "syscon"; + reg = <0x1F04D028 0x004>; + + be,l2-ws-latency = <0>; + be,l2-tag-latency = <0>; + be,l2-data-latency = <1>; + + little-endian; + reg-io-width = <4>; + }; +...
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