[PATCH v7 0/7] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses

* use devm_add_action_or_reset to unprepare clock in case of error (suggested by Paul Cercueil [off-list ref])
* use already existing constants to check for overflow of rd_adj and rd_strobe
* remove clock-names from bindings example and DTS (suggested by Paul Cercueil [off-list ref])
* addition for nemc driver to handle this correctly (contributed by Paul Cercueil [off-list ref])
* make efuse a child node of nemc to avoid problems with overlapping
  reg address ranges (suggested by Paul Cercueil [off-list ref])

PATCH V6 2020-02-26 12:16:07:
* add dependency on CONFIG_OF and select REGMAP_MMIO (suggested by Paul Cercueil [off-list ref])
* add clk_prepare_enable() (suggested by Paul Cercueil [off-list ref])
* inline jz4780_efuse_read_32bytes() since it is only used once
* remove read optimization for full block (suggested by Paul Cercueil [off-list ref])
* simplify calculations for rd_adj and rd_strobe (suggested by Paul Cercueil [off-list ref])
* do calculations for rd_adj and rd_strobe in local variables
* fix overflow check (did allow for 5 bit values although register is 4 bit wide)
* fixes for yaml (sugested by Andreas Kemnade [off-list ref])

PATCH V5 2020-02-22 11:25:35:
* no longer RFC but PATCH
* add yaml bindings (by Andreas Kemnade [off-list ref])
* fixes to yaml (suggested by Rob Herring [off-list ref])

RFC V4 2020-02-17 17:55:35:
* removed read_only for nvmem config because there is no write method
* Kconfig: replaced depends MACH_JZ4780 with MACH_INGENIC
* run through checkpatch and fixed issues
* made use of devm_nvram_register() and get rid of jz4780_efuse_remove()
  (suggested by Srinivas Kandagatla [off-list ref])
* squashed previous patch 1/9 and 2/9 into single (regmap based) driver

RFC V3 2020-02-16 20:20:59:

This series is based on and a follow up for

https://lore.kernel.org/patchwork/cover/868157/

("[v2,0/2] Add efuse driver for Ingenic JZ4780 SoC")

Original authors were
PrasannaKumar Muralidharan [off-list ref]
Mathieu Malaterre [off-list ref]

and there are additions / code improvements by
H. Nikolaus Schaller [off-list ref]
Paul Cercueil [off-list ref]

This setup works, if the dm9000 driver is compiled
as a module.

Therefore it is all RFC level. It is also not completely
checkpatched.


H. Nikolaus Schaller (1):
  MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the
    default MAC address

Paul Cercueil (1):
  memory: jz4780_nemc: Only request IO memory the driver will use

PrasannaKumar Muralidharan (5):
  nvmem: add driver for JZ4780 efuse
  Bindings: nvmem: add bindings for JZ4780 efuse
  Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI
  nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver
  MIPS: DTS: JZ4780: define node for JZ4780 efuse

 .../ABI/testing/sysfs-driver-jz4780-efuse     |  16 ++
 .../bindings/nvmem/ingenic,jz4780-efuse.yaml  |  49 ++++
 MAINTAINERS                                   |   5 +
 arch/mips/boot/dts/ingenic/ci20.dts           |   3 +
 arch/mips/boot/dts/ingenic/jz4780.dtsi        |  19 +-
 drivers/memory/jz4780-nemc.c                  |  15 +-
 drivers/nvmem/Kconfig                         |  12 +
 drivers/nvmem/Makefile                        |   2 +
 drivers/nvmem/jz4780-efuse.c                  | 234 ++++++++++++++++++
 9 files changed, 352 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse
 create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
 create mode 100644 drivers/nvmem/jz4780-efuse.c

-- 
2.23.0

From: Paul Cercueil <paul@crapouillou.net>

The driver only uses the registers up to offset 0x54. Since the EFUSE
registers are in the middle of the NEMC registers, we only request
the registers we will use for now - that way the EFUSE driver can
probe too.

Tested-by: H. Nikolaus Schaller <redacted>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/memory/jz4780-nemc.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c
index b232ed279fc3..647267ea8c63 100644
--- a/drivers/memory/jz4780-nemc.c
+++ b/drivers/memory/jz4780-nemc.c

@@ -8,6 +8,7 @@
 
 #include <linux/clk.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/math64.h>
 #include <linux/of.h>
 #include <linux/of_address.h>

@@ -288,7 +289,19 @@ static int jz4780_nemc_probe(struct platform_device *pdev)
 	nemc->dev = dev;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	nemc->base = devm_ioremap_resource(dev, res);
+
+	/*
+	 * The driver only uses the registers up to offset 0x54. Since the EFUSE
+	 * registers are in the middle of the NEMC registers, we only request
+	 * the registers we will use for now - that way the EFUSE driver can
+	 * probe too.
+	 */
+	if (!devm_request_mem_region(dev, res->start, 0x54, dev_name(dev))) {
+		dev_err(dev, "unable to request I/O memory region\n");
+		return -EBUSY;
+	}
+
+	nemc->base = devm_ioremap(dev, res->start, resource_size(res));
 	if (IS_ERR(nemc->base)) {
 		dev_err(dev, "failed to get I/O memory\n");
 		return PTR_ERR(nemc->base);

-- 
2.23.0

From: PrasannaKumar Muralidharan <redacted>

This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory and nvmem cells.

To fetch for example the MAC address:

dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd

Tested-by: Mathieu Malaterre <redacted>
Signed-off-by: PrasannaKumar Muralidharan <redacted>
Signed-off-by: Mathieu Malaterre <redacted>
Signed-off-by: H. Nikolaus Schaller <redacted>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/nvmem/Kconfig        |  12 ++
 drivers/nvmem/Makefile       |   2 +
 drivers/nvmem/jz4780-efuse.c | 234 +++++++++++++++++++++++++++++++++++
 3 files changed, 248 insertions(+)
 create mode 100644 drivers/nvmem/jz4780-efuse.c

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 35efab1ba8d9..d7b7f6d688e7 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig

@@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU
 	  This is a driver for the SCU On-Chip OTP Controller (OCOTP)
 	  available on i.MX8 SoCs.
 
+config JZ4780_EFUSE
+	tristate "JZ4780 EFUSE Memory Support"
+	depends on MACH_INGENIC || COMPILE_TEST
+	depends on HAS_IOMEM
+	depends on OF
+	select REGMAP_MMIO
+	help
+	  Say Y here to include support for JZ4780 efuse memory found on
+	  all JZ4780 SoC based devices.
+	  To compile this driver as a module, choose M here: the module
+	  will be called nvmem_jz4780_efuse.
+
 config NVMEM_LPC18XX_EEPROM
 	tristate "NXP LPC18XX EEPROM Memory Support"
 	depends on ARCH_LPC18XX || COMPILE_TEST

diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 6b466cd1427b..65a268d17807 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile

@@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP)	+= nvmem-imx-ocotp.o
 nvmem-imx-ocotp-y		:= imx-ocotp.o
 obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU)	+= nvmem-imx-ocotp-scu.o
 nvmem-imx-ocotp-scu-y		:= imx-ocotp-scu.o
+obj-$(CONFIG_JZ4780_EFUSE)		+= nvmem_jz4780_efuse.o
+nvmem_jz4780_efuse-y		:= jz4780-efuse.o
 obj-$(CONFIG_NVMEM_LPC18XX_EEPROM)	+= nvmem_lpc18xx_eeprom.o
 nvmem_lpc18xx_eeprom-y	:= lpc18xx_eeprom.o
 obj-$(CONFIG_NVMEM_LPC18XX_OTP)	+= nvmem_lpc18xx_otp.o

diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c
new file mode 100644
index 000000000000..4e9dd340e33a
--- /dev/null
+++ b/drivers/nvmem/jz4780-efuse.c

@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * JZ4780 EFUSE Memory Support driver
+ *
+ * Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ * Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
+ */
+
+/*
+ * Currently supports JZ4780 efuse which has 8K programmable bit.
+ * Efuse is separated into seven segments as below:
+ *
+ * -----------------------------------------------------------------------
+ * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
+ * -----------------------------------------------------------------------
+ *
+ * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
+ * which reads/writes based on strobes. The strobe is configured in the config
+ * register and is based on number of cycles of the bus clock.
+ *
+ * Driver supports read only as the writes are done in the Factory.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/timer.h>
+
+#define JZ_EFUCTRL		(0x0)	/* Control Register */
+#define JZ_EFUCFG		(0x4)	/* Configure Register*/
+#define JZ_EFUSTATE		(0x8)	/* Status Register */
+#define JZ_EFUDATA(n)		(0xC + (n) * 4)
+
+/* We read 32 byte chunks to avoid complexity in the driver. */
+#define JZ_EFU_READ_SIZE 32
+
+#define EFUCTRL_ADDR_MASK	0x3FF
+#define EFUCTRL_ADDR_SHIFT	21
+#define EFUCTRL_LEN_MASK	0x1F
+#define EFUCTRL_LEN_SHIFT	16
+#define EFUCTRL_PG_EN		BIT(15)
+#define EFUCTRL_WR_EN		BIT(1)
+#define EFUCTRL_RD_EN		BIT(0)
+
+#define EFUCFG_INT_EN		BIT(31)
+#define EFUCFG_RD_ADJ_MASK	0xF
+#define EFUCFG_RD_ADJ_SHIFT	20
+#define EFUCFG_RD_STR_MASK	0xF
+#define EFUCFG_RD_STR_SHIFT	16
+#define EFUCFG_WR_ADJ_MASK	0xF
+#define EFUCFG_WR_ADJ_SHIFT	12
+#define EFUCFG_WR_STR_MASK	0xFFF
+#define EFUCFG_WR_STR_SHIFT	0
+
+#define EFUSTATE_WR_DONE	BIT(1)
+#define EFUSTATE_RD_DONE	BIT(0)
+
+struct jz4780_efuse {
+	struct device *dev;
+	struct regmap *map;
+	struct clk *clk;
+};
+
+/* main entry point */
+static int jz4780_efuse_read(void *context, unsigned int offset,
+			     void *val, size_t bytes)
+{
+	struct jz4780_efuse *efuse = context;
+
+	while (bytes > 0) {
+		unsigned int start = offset & ~(JZ_EFU_READ_SIZE - 1);
+		unsigned int chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
+					 - offset);
+		char buf[JZ_EFU_READ_SIZE];
+		unsigned int tmp;
+		u32 ctrl;
+		int ret;
+
+		ctrl = (start << EFUCTRL_ADDR_SHIFT)
+			| ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
+			| EFUCTRL_RD_EN;
+
+		regmap_update_bits(efuse->map, JZ_EFUCTRL,
+				   (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
+				   (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
+				   EFUCTRL_PG_EN | EFUCTRL_WR_EN |
+				   EFUCTRL_RD_EN,
+				   ctrl);
+
+		ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
+					       tmp, tmp & EFUSTATE_RD_DONE,
+					       1 * MSEC_PER_SEC,
+					       50 * MSEC_PER_SEC);
+		if (ret < 0) {
+			dev_err(efuse->dev, "Time out while reading efuse data");
+			return ret;
+		}
+
+		ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
+				       buf, JZ_EFU_READ_SIZE / sizeof(u32));
+		if (ret < 0)
+			return ret;
+
+		memcpy(val, &buf[offset - start], chunk);
+
+		val += chunk;
+		offset += chunk;
+		bytes -= chunk;
+	}
+
+	return 0;
+}
+
+static struct nvmem_config jz4780_efuse_nvmem_config = {
+	.name = "jz4780-efuse",
+	.size = 1024,
+	.word_size = 1,
+	.stride = 1,
+	.owner = THIS_MODULE,
+	.reg_read = jz4780_efuse_read,
+};
+
+static const struct regmap_config jz4780_efuse_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.max_register = JZ_EFUDATA(7),
+};
+
+static int jz4780_efuse_probe(struct platform_device *pdev)
+{
+	struct nvmem_device *nvmem;
+	struct jz4780_efuse *efuse;
+	struct nvmem_config cfg;
+	unsigned long clk_rate;
+	unsigned long rd_adj;
+	unsigned long rd_strobe;
+	struct device *dev = &pdev->dev;
+	void __iomem *regs;
+	int ret;
+
+	efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
+	if (!efuse)
+		return -ENOMEM;
+
+	regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	efuse->map = devm_regmap_init_mmio(dev, regs,
+					   &jz4780_efuse_regmap_config);
+	if (IS_ERR(efuse->map))
+		return PTR_ERR(efuse->map);
+
+	efuse->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(efuse->clk))
+		return PTR_ERR(efuse->clk);
+
+	ret = clk_prepare_enable(efuse->clk);
+	if (ret < 0)
+		return ret;
+
+	ret = devm_add_action_or_reset(&pdev->dev,
+				       &clk_disable_unprepare,
+				       efuse->clk);
+	if (ret < 0)
+		return ret;
+
+	clk_rate = clk_get_rate(efuse->clk);
+
+	efuse->dev = dev;
+
+	/*
+	 * rd_adj and rd_strobe are 4 bit values
+	 * conditions:
+	 *   bus clk_period * (rd_adj + 1) > 6.5ns
+	 *   bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
+	 *   i.e. rd_adj >= 6.5ns / clk_period
+	 *   i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
+	 * constants:
+	 *   1 / 6.5ns == 153846154 Hz
+	 *   1 / 35ns == 28571429 Hz
+	 */
+
+	rd_adj = clk_rate / 153846154;
+	rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
+
+	if (rd_adj > EFUCFG_RD_ADJ_MASK ||
+	    rd_strobe > EFUCFG_RD_STR_MASK) {
+		dev_err(&pdev->dev, "Cannot set clock configuration\n");
+		return -EINVAL;
+	}
+
+	regmap_update_bits(efuse->map, JZ_EFUCFG,
+			   (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
+			   (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
+			   (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
+			   (rd_strobe << EFUCFG_RD_STR_SHIFT));
+
+	cfg = jz4780_efuse_nvmem_config;
+	cfg.dev = &pdev->dev;
+	cfg.priv = efuse;
+
+	nvmem = devm_nvmem_register(dev, &cfg);
+	if (IS_ERR(nvmem))
+		return PTR_ERR(nvmem);
+
+	return 0;
+}
+
+static const struct of_device_id jz4780_efuse_match[] = {
+	{ .compatible = "ingenic,jz4780-efuse" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+
+static struct platform_driver jz4780_efuse_driver = {
+	.probe  = jz4780_efuse_probe,
+	.driver = {
+		.name = "jz4780-efuse",
+		.of_match_table = jz4780_efuse_match,
+	},
+};
+module_platform_driver(jz4780_efuse_driver);
+
+MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
+MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
+MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
+MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");

-- 
2.23.0

Hi Nikolaus,

Le ven., févr. 28, 2020 at 14:58, H. Nikolaus Schaller 
[off-list ref] a écrit :

That's what I thought, this does not build:

  CC      drivers/nvmem/jz4780-efuse.o
drivers/nvmem/jz4780-efuse.c: In function 'jz4780_efuse_probe':
drivers/nvmem/jz4780-efuse.c:168:12: error: passing argument 2 of 
'devm_add_action_or_reset' from incompatible pointer type 
[-Werror=incompatible-pointer-types]
  168 |            &clk_disable_unprepare,
      |            ^~~~~~~~~~~~~~~~~~~~~~
      |            |
      |            void (*)(struct clk *)
In file included from ./include/linux/platform_device.h:13,
                 from drivers/nvmem/jz4780-efuse.c:29:
./include/linux/device.h:256:16: note: expected 'void (*)(void *)' but 
argument is of type 'void (*)(struct clk *)'
  256 |         void (*action)(void *), void *data)
      |         ~~~~~~~^~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
make[2]: *** [scripts/Makefile.build:268: drivers/nvmem/jz4780-efuse.o] 
Error 1
make[1]: *** [scripts/Makefile.build:505: drivers/nvmem] Error 2
make: *** [Makefile:1681: drivers] Error 2


You need a local function of type 'void foo(void *data)' that just 
calls clk_disable_unprepare(data) and the compiler will be happy.
(btw - no need to deference functions pointers, since they are already 
pointers)

With that said, I expect you to at least compile-test the patchset 
before sending it upstream...

The rest of the patch looks good, so just fix that, and it'll be good 
to go.

Cheers,
-Paul

+	if (ret < 0)
+		return ret;
+
+	clk_rate = clk_get_rate(efuse->clk);
+
+	efuse->dev = dev;
+
+	/*
+	 * rd_adj and rd_strobe are 4 bit values
+	 * conditions:
+	 *   bus clk_period * (rd_adj + 1) > 6.5ns
+	 *   bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
+	 *   i.e. rd_adj >= 6.5ns / clk_period
+	 *   i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
+	 * constants:
+	 *   1 / 6.5ns == 153846154 Hz
+	 *   1 / 35ns == 28571429 Hz
+	 */
+
+	rd_adj = clk_rate / 153846154;
+	rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
+
+	if (rd_adj > EFUCFG_RD_ADJ_MASK ||
+	    rd_strobe > EFUCFG_RD_STR_MASK) {
+		dev_err(&pdev->dev, "Cannot set clock configuration\n");
+		return -EINVAL;
+	}
+
+	regmap_update_bits(efuse->map, JZ_EFUCFG,
+			   (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
+			   (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
+			   (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
+			   (rd_strobe << EFUCFG_RD_STR_SHIFT));
+
+	cfg = jz4780_efuse_nvmem_config;
+	cfg.dev = &pdev->dev;
+	cfg.priv = efuse;
+
+	nvmem = devm_nvmem_register(dev, &cfg);
+	if (IS_ERR(nvmem))
+		return PTR_ERR(nvmem);
+
+	return 0;
+}
+
+static const struct of_device_id jz4780_efuse_match[] = {
+	{ .compatible = "ingenic,jz4780-efuse" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+
+static struct platform_driver jz4780_efuse_driver = {
+	.probe  = jz4780_efuse_probe,
+	.driver = {
+		.name = "jz4780-efuse",
+		.of_match_table = jz4780_efuse_match,
+	},
+};
+module_platform_driver(jz4780_efuse_driver);
+
+MODULE_AUTHOR("PrasannaKumar Muralidharan 
[off-list ref]");
+MODULE_AUTHOR("H. Nikolaus Schaller [off-list ref]");
+MODULE_AUTHOR("Paul Cercueil [off-list ref]");
+MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
--
2.23.0

Am 28.02.2020 um 15:48 schrieb Paul Cercueil [off-list ref]:

Hi Nikolaus,

Le ven., févr. 28, 2020 at 14:58, H. Nikolaus Schaller [off-list ref] a écrit :

quoted

From: PrasannaKumar Muralidharan <redacted>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory and nvmem cells.
To fetch for example the MAC address:
dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd
Tested-by: Mathieu Malaterre <redacted>
Signed-off-by: PrasannaKumar Muralidharan <redacted>
Signed-off-by: Mathieu Malaterre <redacted>
Signed-off-by: H. Nikolaus Schaller <redacted>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/nvmem/Kconfig        |  12 ++
drivers/nvmem/Makefile       |   2 +
drivers/nvmem/jz4780-efuse.c | 234 +++++++++++++++++++++++++++++++++++
3 files changed, 248 insertions(+)
create mode 100644 drivers/nvmem/jz4780-efuse.c

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 35efab1ba8d9..d7b7f6d688e7 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig

@@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU

	  This is a driver for the SCU On-Chip OTP Controller (OCOTP)
	  available on i.MX8 SoCs.
+config JZ4780_EFUSE
+	tristate "JZ4780 EFUSE Memory Support"
+	depends on MACH_INGENIC || COMPILE_TEST
+	depends on HAS_IOMEM
+	depends on OF
+	select REGMAP_MMIO
+	help
+	  Say Y here to include support for JZ4780 efuse memory found on
+	  all JZ4780 SoC based devices.
+	  To compile this driver as a module, choose M here: the module
+	  will be called nvmem_jz4780_efuse.
+
config NVMEM_LPC18XX_EEPROM
	tristate "NXP LPC18XX EEPROM Memory Support"
	depends on ARCH_LPC18XX || COMPILE_TEST

diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 6b466cd1427b..65a268d17807 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile

@@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP)	+= nvmem-imx-ocotp.o

nvmem-imx-ocotp-y		:= imx-ocotp.o
obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU)	+= nvmem-imx-ocotp-scu.o
nvmem-imx-ocotp-scu-y		:= imx-ocotp-scu.o
+obj-$(CONFIG_JZ4780_EFUSE)		+= nvmem_jz4780_efuse.o
+nvmem_jz4780_efuse-y		:= jz4780-efuse.o
obj-$(CONFIG_NVMEM_LPC18XX_EEPROM)	+= nvmem_lpc18xx_eeprom.o
nvmem_lpc18xx_eeprom-y	:= lpc18xx_eeprom.o
obj-$(CONFIG_NVMEM_LPC18XX_OTP)	+= nvmem_lpc18xx_otp.o

diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c
new file mode 100644
index 000000000000..4e9dd340e33a
--- /dev/null
+++ b/drivers/nvmem/jz4780-efuse.c

@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * JZ4780 EFUSE Memory Support driver
+ *
+ * Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ * Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
+ */
+
+/*
+ * Currently supports JZ4780 efuse which has 8K programmable bit.
+ * Efuse is separated into seven segments as below:
+ *
+ * -----------------------------------------------------------------------
+ * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
+ * -----------------------------------------------------------------------
+ *
+ * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
+ * which reads/writes based on strobes. The strobe is configured in the config
+ * register and is based on number of cycles of the bus clock.
+ *
+ * Driver supports read only as the writes are done in the Factory.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/timer.h>
+
+#define JZ_EFUCTRL		(0x0)	/* Control Register */
+#define JZ_EFUCFG		(0x4)	/* Configure Register*/
+#define JZ_EFUSTATE		(0x8)	/* Status Register */
+#define JZ_EFUDATA(n)		(0xC + (n) * 4)
+
+/* We read 32 byte chunks to avoid complexity in the driver. */
+#define JZ_EFU_READ_SIZE 32
+
+#define EFUCTRL_ADDR_MASK	0x3FF
+#define EFUCTRL_ADDR_SHIFT	21
+#define EFUCTRL_LEN_MASK	0x1F
+#define EFUCTRL_LEN_SHIFT	16
+#define EFUCTRL_PG_EN		BIT(15)
+#define EFUCTRL_WR_EN		BIT(1)
+#define EFUCTRL_RD_EN		BIT(0)
+
+#define EFUCFG_INT_EN		BIT(31)
+#define EFUCFG_RD_ADJ_MASK	0xF
+#define EFUCFG_RD_ADJ_SHIFT	20
+#define EFUCFG_RD_STR_MASK	0xF
+#define EFUCFG_RD_STR_SHIFT	16
+#define EFUCFG_WR_ADJ_MASK	0xF
+#define EFUCFG_WR_ADJ_SHIFT	12
+#define EFUCFG_WR_STR_MASK	0xFFF
+#define EFUCFG_WR_STR_SHIFT	0
+
+#define EFUSTATE_WR_DONE	BIT(1)
+#define EFUSTATE_RD_DONE	BIT(0)
+
+struct jz4780_efuse {
+	struct device *dev;
+	struct regmap *map;
+	struct clk *clk;
+};
+
+/* main entry point */
+static int jz4780_efuse_read(void *context, unsigned int offset,
+			     void *val, size_t bytes)
+{
+	struct jz4780_efuse *efuse = context;
+
+	while (bytes > 0) {
+		unsigned int start = offset & ~(JZ_EFU_READ_SIZE - 1);
+		unsigned int chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
+					 - offset);
+		char buf[JZ_EFU_READ_SIZE];
+		unsigned int tmp;
+		u32 ctrl;
+		int ret;
+
+		ctrl = (start << EFUCTRL_ADDR_SHIFT)
+			| ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
+			| EFUCTRL_RD_EN;
+
+		regmap_update_bits(efuse->map, JZ_EFUCTRL,
+				   (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
+				   (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
+				   EFUCTRL_PG_EN | EFUCTRL_WR_EN |
+				   EFUCTRL_RD_EN,
+				   ctrl);
+
+		ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
+					       tmp, tmp & EFUSTATE_RD_DONE,
+					       1 * MSEC_PER_SEC,
+					       50 * MSEC_PER_SEC);
+		if (ret < 0) {
+			dev_err(efuse->dev, "Time out while reading efuse data");
+			return ret;
+		}
+
+		ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
+				       buf, JZ_EFU_READ_SIZE / sizeof(u32));
+		if (ret < 0)
+			return ret;
+
+		memcpy(val, &buf[offset - start], chunk);
+
+		val += chunk;
+		offset += chunk;
+		bytes -= chunk;
+	}
+
+	return 0;
+}
+
+static struct nvmem_config jz4780_efuse_nvmem_config = {
+	.name = "jz4780-efuse",
+	.size = 1024,
+	.word_size = 1,
+	.stride = 1,
+	.owner = THIS_MODULE,
+	.reg_read = jz4780_efuse_read,
+};
+
+static const struct regmap_config jz4780_efuse_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.max_register = JZ_EFUDATA(7),
+};
+
+static int jz4780_efuse_probe(struct platform_device *pdev)
+{
+	struct nvmem_device *nvmem;
+	struct jz4780_efuse *efuse;
+	struct nvmem_config cfg;
+	unsigned long clk_rate;
+	unsigned long rd_adj;
+	unsigned long rd_strobe;
+	struct device *dev = &pdev->dev;
+	void __iomem *regs;
+	int ret;
+
+	efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
+	if (!efuse)
+		return -ENOMEM;
+
+	regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	efuse->map = devm_regmap_init_mmio(dev, regs,
+					   &jz4780_efuse_regmap_config);
+	if (IS_ERR(efuse->map))
+		return PTR_ERR(efuse->map);
+
+	efuse->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(efuse->clk))
+		return PTR_ERR(efuse->clk);
+
+	ret = clk_prepare_enable(efuse->clk);
+	if (ret < 0)
+		return ret;
+
+	ret = devm_add_action_or_reset(&pdev->dev,
+				       &clk_disable_unprepare,
+				       efuse->clk);

That's what I thought, this does not build:

CC      drivers/nvmem/jz4780-efuse.o
drivers/nvmem/jz4780-efuse.c: In function 'jz4780_efuse_probe':
drivers/nvmem/jz4780-efuse.c:168:12: error: passing argument 2 of 'devm_add_action_or_reset' from incompatible pointer type [-Werror=incompatible-pointer-types]
168 |            &clk_disable_unprepare,
    |            ^~~~~~~~~~~~~~~~~~~~~~
    |            |
    |            void (*)(struct clk *)
In file included from ./include/linux/platform_device.h:13,
               from drivers/nvmem/jz4780-efuse.c:29:
./include/linux/device.h:256:16: note: expected 'void (*)(void *)' but argument is of type 'void (*)(struct clk *)'
256 |         void (*action)(void *), void *data)
    |         ~~~~~~~^~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
make[2]: *** [scripts/Makefile.build:268: drivers/nvmem/jz4780-efuse.o] Error 1
make[1]: *** [scripts/Makefile.build:505: drivers/nvmem] Error 2
make: *** [Makefile:1681: drivers] Error 2


You need a local function of type 'void foo(void *data)' that just calls clk_disable_unprepare(data) and the compiler will be happy.
(btw - no need to deference functions pointers, since they are already pointers)

Well, this asks for a devm_clk_enable_prepare but it was apparently rejected...

https://lore.kernel.org/patchwork/patch/755667/

With that said, I expect you to at least compile-test the patchset before sending it upstream...

I have compiled and tested it on real hardware. But missed the warning because my cross-compiler seems to emit a warning only.

Sorry, I don't have a good day and after 7 rounds one wants to get things through the door and with least effort as quick as possible :)

BR,
Nikolaus

From: PrasannaKumar Muralidharan <redacted>

This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory and the
ethernet mac address for the davicom dm9000 chip on the CI20 board.

It also changes the nemc ranges definition to give the driver
access to the efuse registers, which are in the middle of the
nemc reg range.

Tested-by: Mathieu Malaterre <redacted>
Signed-off-by: PrasannaKumar Muralidharan <redacted>
Signed-off-by: Mathieu Malaterre <redacted>
Signed-off-by: H. Nikolaus Schaller <redacted>
---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index f928329b034b..79f90a5b0415 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi

@@ -357,11 +357,12 @@
 	};
 
 	nemc: nemc@13410000 {
-		compatible = "ingenic,jz4780-nemc";
+		compatible = "ingenic,jz4780-nemc", "simple-mfd";
 		reg = <0x13410000 0x10000>;
 		#address-cells = <2>;
 		#size-cells = <1>;
-		ranges = <1 0 0x1b000000 0x1000000
+		ranges = <0 0 0x13410000 0x10000
+			  1 0 0x1b000000 0x1000000
 			  2 0 0x1a000000 0x1000000
 			  3 0 0x19000000 0x1000000
 			  4 0 0x18000000 0x1000000

@@ -371,6 +372,20 @@
 		clocks = <&cgu JZ4780_CLK_NEMC>;
 
 		status = "disabled";
+
+		efuse: efuse@d0 {
+			reg = <0 0xd0 0x30>;
+			compatible = "ingenic,jz4780-efuse";
+
+			clocks = <&cgu JZ4780_CLK_AHB2>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			eth0_addr: eth-mac-addr@0x22 {
+				reg = <0x22 0x6>;
+			};
+		};
 	};
 
 	dma: dma@13420000 {

-- 
2.23.0

From: PrasannaKumar Muralidharan <redacted>

This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory.

Tested-by: Mathieu Malaterre <redacted>
Signed-off-by: PrasannaKumar Muralidharan <redacted>
Signed-off-by: Mathieu Malaterre <redacted>
---
 .../ABI/testing/sysfs-driver-jz4780-efuse        | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse

diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse
new file mode 100644
index 000000000000..bb6f5d6ceea0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse

@@ -0,0 +1,16 @@
+What:		/sys/devices/*/<our-device>/nvmem
+Date:		December 2017
+Contact:	PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+Description:	read-only access to the efuse on the Ingenic JZ4780 SoC
+		The SoC has a one time programmable 8K efuse that is
+		split into segments. The driver supports read only.
+		The segments are
+		0x000   64 bit Random Number
+		0x008  128 bit Ingenic Chip ID
+		0x018  128 bit Customer ID
+		0x028 3520 bit Reserved
+		0x1E0    8 bit Protect Segment
+		0x1E1 2296 bit HDMI Key
+		0x300 2048 bit Security boot key
+Users:		any user space application which wants to read the Chip
+		and Customer ID

-- 
2.23.0

There is a unique MAC address programmed into the eFuses
of the JZ4780 chip in the CI20 factory. By using this
for initializing the DM9000 Ethernet controller, every
CI20 board has an individual - but stable - MAC address
and DHCP can assign stable IP addresses.

Signed-off-by: H. Nikolaus Schaller <redacted>
---
 arch/mips/boot/dts/ingenic/ci20.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 37b93166bf22..6dc1f9eeff00 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts

@@ -355,6 +355,9 @@
 
 		interrupt-parent = <&gpe>;
 		interrupts = <19 4>;
+
+		nvmem-cells = <&eth0_addr>;
+		nvmem-cell-names = "mac-address";
 	};
 };
 

-- 
2.23.0

From: PrasannaKumar Muralidharan <redacted>

This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory.

Tested-by: Mathieu Malaterre <redacted>
Signed-off-by: PrasannaKumar Muralidharan <redacted>
Signed-off-by: Mathieu Malaterre <redacted>
---
 MAINTAINERS | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index fcd79fc38928..fcb8d89c2b2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS

@@ -8271,6 +8271,11 @@ M:	Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
 S:	Maintained
 F:	drivers/dma/dma-jz4780.c
 
+INGENIC JZ4780 EFUSE Driver
+M:	PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+S:	Maintained
+F:	drivers/nvmem/jz4780-efuse.c
+
 INGENIC JZ4780 NAND DRIVER
 M:	Harvey Hunt <harveyhuntnexus@gmail.com>
 L:	linux-mtd@lists.infradead.org

-- 
2.23.0

From: PrasannaKumar Muralidharan <redacted>

This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory.

Tested-by: Mathieu Malaterre <redacted>
Signed-off-by: PrasannaKumar Muralidharan <redacted>
Signed-off-by: Mathieu Malaterre <redacted>
Signed-off-by: H. Nikolaus Schaller <redacted>
[converted to yaml]
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
---
 .../bindings/nvmem/ingenic,jz4780-efuse.yaml  | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml

diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
new file mode 100644
index 000000000000..ce6690c50a34
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic JZ EFUSE driver bindings
+
+maintainers:
+  - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - ingenic,jz4780-efuse
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    # Handle for the ahb for the efuse.
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ahb2
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/jz4780-cgu.h>
+
+    efuse@134100d0 {
+        compatible = "ingenic,jz4780-efuse";
+        reg = <0x134100d0 0x2c>;
+
+        clocks = <&cgu JZ4780_CLK_AHB2>;
+    };
+
+...

-- 
2.23.0

Hi Nikolaus,


Le ven., févr. 28, 2020 at 14:58, H. Nikolaus Schaller 
[off-list ref] a écrit :

You still have clock-names here. You can remove it completely.

+
+required:
+  - compatible
+  - reg
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/jz4780-cgu.h>
+
+    efuse@134100d0 {
+        compatible = "ingenic,jz4780-efuse";
+        reg = <0x134100d0 0x2c>;
+
+        clocks = <&cgu JZ4780_CLK_AHB2>;
+    };
+
+...
--
2.23.0

Am 28.02.2020 um 15:40 schrieb Paul Cercueil [off-list ref]:

Hi Nikolaus,


Le ven., févr. 28, 2020 at 14:58, H. Nikolaus Schaller [off-list ref] a écrit :

quoted

From: PrasannaKumar Muralidharan <redacted>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre <redacted>
Signed-off-by: PrasannaKumar Muralidharan <redacted>
Signed-off-by: Mathieu Malaterre <redacted>
Signed-off-by: H. Nikolaus Schaller <redacted>
[converted to yaml]
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
---
.../bindings/nvmem/ingenic,jz4780-efuse.yaml  | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml

diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
new file mode 100644
index 000000000000..ce6690c50a34
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic JZ EFUSE driver bindings
+
+maintainers:
+  - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - ingenic,jz4780-efuse
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    # Handle for the ahb for the efuse.
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ahb2

You still have clock-names here. You can remove it completely.

I have just removed them from required: and the examples: because
I think they are optional. Or are they forbidden?

quoted

+
+required:
+  - compatible
+  - reg
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/jz4780-cgu.h>
+
+    efuse@134100d0 {
+        compatible = "ingenic,jz4780-efuse";
+        reg = <0x134100d0 0x2c>;
+
+        clocks = <&cgu JZ4780_CLK_AHB2>;
+    };
+
+...
--
2.23.0

BR,
Nikolaus

Le ven., févr. 28, 2020 at 15:47, H. Nikolaus Schaller 
[off-list ref] a écrit :

quoted

 Am 28.02.2020 um 15:40 schrieb Paul Cercueil [off-list ref]:

 Hi Nikolaus,


 Le ven., févr. 28, 2020 at 14:58, H. Nikolaus Schaller 
[off-list ref] a écrit :

quoted

 From: PrasannaKumar Muralidharan [off-list ref]
 This patch brings support for the JZ4780 efuse. Currently it only 
exposes
 a read only access to the entire 8K bits efuse memory.
 Tested-by: Mathieu Malaterre [off-list ref]
 Signed-off-by: PrasannaKumar Muralidharan 
[off-list ref]
 Signed-off-by: Mathieu Malaterre [off-list ref]
 Signed-off-by: H. Nikolaus Schaller [off-list ref]
 [converted to yaml]
 Signed-off-by: Andreas Kemnade [off-list ref]
 ---
 .../bindings/nvmem/ingenic,jz4780-efuse.yaml  | 49 
+++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
 diff --git 
a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml 
b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
 new file mode 100644
 index 000000000000..ce6690c50a34
 --- /dev/null
 +++ 
b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
 @@ -0,0 +1,49 @@
 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
 +%YAML 1.2
 +---
 +$id: 
http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
 +$schema: http://devicetree.org/meta-schemas/core.yaml#
 +
 +title: Ingenic JZ EFUSE driver bindings
 +
 +maintainers:
 +  - PrasannaKumar Muralidharan [off-list ref]
 +
 +allOf:
 +  - $ref: "nvmem.yaml#"
 +
 +properties:
 +  compatible:
 +    enum:
 +      - ingenic,jz4780-efuse
 +
 +  reg:
 +    maxItems: 1
 +
 +  clocks:
 +    # Handle for the ahb for the efuse.
 +    maxItems: 1
 +
 +  clock-names:
 +    items:
 +      - const: ahb2

 You still have clock-names here. You can remove it completely.

I have just removed them from required: and the examples: because
I think they are optional. Or are they forbidden?

The driver does not get its clock by name, it just takes the first one. 
So having 'clock-names' in the binding is just not needed.

-Paul

quoted

quoted

 +
 +required:
 +  - compatible
 +  - reg
 +  - clocks
 +
 +unevaluatedProperties: false
 +
 +examples:
 +  - |
 +    #include <dt-bindings/clock/jz4780-cgu.h>
 +
 +    efuse@134100d0 {
 +        compatible = "ingenic,jz4780-efuse";
 +        reg = <0x134100d0 0x2c>;
 +
 +        clocks = <&cgu JZ4780_CLK_AHB2>;
 +    };
 +
 +...
 --
 2.23.0

BR,
Nikolaus