On Fri, 31 Jan 2020 09:11:10 -0600, Dan Murphy wrote:

Set the speed optimization bit on the DP83867 PHY.
This feature can also be strapped on the 64 pin PHY devices
but the 48 pin devices do not have the strap pin available to enable
this feature in the hardware.  PHY team suggests to have this bit set.

With this bit set the PHY will auto negotiate and report the link
parameters in the PHYSTS register and not in the BMCR.  So we need to
over ride the genphy_read_status with a DP83867 specific read status.

Signed-off-by: Dan Murphy <redacted>

While we wait for the PHY folk to take a look, could you please 
provide a Fixes tag?