Re: [PATCH v3 01/14] dt-bindings: phy: Convert Cadence MHDP PHY bindings to YAML.
From: Rob Herring <robh@kernel.org>
Date: 2020-01-27 16:25:37
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On Wed, Jan 22, 2020 at 11:45:05AM +0100, Yuti Amonkar wrote:
- Convert the MHDP PHY devicetree bindings to yaml schemas. - Rename DP PHY to have generic Torrent PHY nomrnclature. - Add Torrent PHY reference clock bindings. - Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy". This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case Signed-off-by: Yuti Amonkar <redacted> --- .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 -------- .../bindings/phy/phy-cadence-torrent.yaml | 82 ++++++++++++++++++++++ 2 files changed, 82 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
quoted hunk ↗ jump to hunk
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml new file mode 100644 index 0000000..eb633d7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml@@ -0,0 +1,82 @@
Missing SPDX tag. As Cadence is the only contributor to the old doc, please relicense to dual license: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence Torrent SD0801 PHY binding for DisplayPort + +description: + This binding describes the Cadence SD0801 PHY (also known as Torrent PHY) + hardware included with the Cadence MHDP DisplayPort controller. + +maintainers: + - Swapnil Jakhade [off-list ref] + - Yuti Amonkar [off-list ref] + +properties: + compatible: + const: cdns,torrent-phy + + clocks: + maxItems: 1 + description: + PHY reference clock. Must contain an entry in clock-names. + + clock-names: + const: refclk + + reg: + minItems: 1 + maxItems: 2 + items: + - description: Offset of the Torrent PHY configuration registers. + - description: Offset of the DPTX PHY configuration registers. + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: torrent_phy + - const: dptx_phy + + "#phy-cells": + const: 0 + + num_lanes:
Given you don't care about compatibility, please make this 'num-lanes'.
+ description: + Number of DisplayPort lanes. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 2, 4]
If optional, then define a default.
+ + max_bit_rate:
And this 'max-bit-rate-mbps'.
+ description: + Maximum DisplayPort link bit rate to use, in Mbps + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
default?
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ dp_phy: phy@f0fb500000 {
+ compatible = "cdns,torrent-phy";
+ reg = <0xf0 0xfb500000 0x0 0x00100000>,
+ <0xf0 0xfb030a00 0x0 0x00000040>;
+ reg-names = "torrent_phy", "dptx_phy";
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ clocks = <&ref_clk>;
+ clock-names = "refclk";
+ };
+...
--
2.4.5