Thread (23 messages) 23 messages, 4 authors, 2020-01-06

Re: [PATCH v3 07/10] clk: clock-wizard: Update the fixed factor divisors

From: Stephen Boyd <sboyd@kernel.org>
Date: 2020-01-05 20:00:16
Also in: linux-clk, lkml

Quoting shubhrajyoti.datta@gmail.com (2019-11-27 22:36:14)
quoted hunk ↗ jump to hunk
From: Shubhrajyoti Datta <redacted>

Update the fixed factor clock registration to register the divisors.

Signed-off-by: Shubhrajyoti Datta <redacted>
---
 drivers/clk/clk-xlnx-clock-wizard.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index 4c6155b..75ea745 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -491,9 +491,11 @@ static int clk_wzrd_probe(struct platform_device *pdev)
        u32 reg, reg_f, mult;
        unsigned long rate;
        const char *clk_name;
+       void __iomem *ctrl_reg;
        struct clk_wzrd *clk_wzrd;
        struct resource *mem;
        int outputs;
+       unsigned long flags = 0;
        struct device_node *np = pdev->dev.of_node;
 
        clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -564,19 +566,22 @@ static int clk_wzrd_probe(struct platform_device *pdev)
                goto err_disable_clk;
        }
 
-       /* register div */
-       reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
-                       WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
+       outputs = of_property_count_strings(np, "clock-output-names");
+       if (outputs == 1)
+               flags = CLK_SET_RATE_PARENT;
What does the number of clk outputs have to do with the ability to
change the rate of a parent clk? The commit text doesn't inform me of
what this is for either. Please help us understand.
        clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
        if (!clk_name) {
                ret = -ENOMEM;
                goto err_rm_int_clk;
        }
 
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