[PATCH 3/3] arm64: dts: qcom: sc7180: Add Last level cache controller node
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LANDED
From: Sai Prakash Ranjan <hidden>
Date: 2019-12-11 04:30:50
Also in:
linux-arm-msm, lkml
Subsystem:
arm/qualcomm chromebook support, arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
Landed in mainline as c831fa299996 on 2019-12-11.
Add device tree node for LLCC aka system cache controller for SC7180 SoC. Signed-off-by: Sai Prakash Ranjan <redacted> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index a6773ad3738b..e1567109adc4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi@@ -911,6 +911,13 @@ status = "disabled"; }; + system-cache-controller@9200000 { + compatible = "qcom,sc7180-llcc"; + reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, ---
This patch depends on the llcc binding change already reviewed at: - https://patchwork.kernel.org/patch/11246055/ -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation