Re: [PATCH] arm64: dts: imx8mq: Add CAAM node
From: Horia Geanta <horia.geanta@nxp.com>
Date: 2019-09-06 10:37:00
Also in:
linux-arm-kernel, linux-crypto, lkml
On 8/31/2019 12:01 AM, Andrey Smirnov wrote:
Add node for CAAM - Cryptographic Acceleration and Assurance Module. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Andrey Smirnov <redacted> Cc: Cory Tusar <redacted> Cc: Chris Healy <redacted> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Iuliana Prodan <redacted> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Shawn: Just a bit of a context: as per this thread https://lore.kernel.org/linux-crypto/20190830131547.GA27480@gondor.apana.org.au/ (local) I am hoping I can get and Ack from you for this patch, so it can go via cryptodev tree.
Could we please get an Ack in time for v5.4? Thanks, Horia
quoted hunk
Thanks, Andrey Smirnov arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+)diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d09b808eff87..752d5a61878c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi@@ -728,6 +728,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_AHB>, + <&clk IMX8MQ_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a20000 0x10000>;