Thread (10 messages) 10 messages, 2 authors, 2019-08-21

Re: [PATCH v5 2/7] dt-bindings: display: msm: gmu: add optional ocmem property

From: Rob Herring <hidden>
Date: 2019-08-21 19:26:06
Also in: dri-devel, linux-arm-msm, lkml

On Mon, Aug 05, 2019 at 08:22:24PM -0400, Brian Masney wrote:
quoted hunk ↗ jump to hunk
Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
must use the On Chip MEMory (OCMEM) in order to be functional. Add the
optional ocmem property to the Adreno Graphics Management Unit bindings.

Signed-off-by: Brian Masney <redacted>
---
Changes since v4:
- None

Changes since v3:
- correct link to qcom,ocmem.yaml

Changes since v2:
- Add a3xx example with OCMEM

Changes since v1:
- None

 .../devicetree/bindings/display/msm/gmu.txt   | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt
index 90af5b0a56a9..672d557caba4 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
@@ -31,6 +31,10 @@ Required properties:
 - iommus: phandle to the adreno iommu
 - operating-points-v2: phandle to the OPP operating points
 
+Optional properties:
+- ocmem: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
+         SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
Sigh, to repeat my comment on v1 and v3:

We already have a couple of similar properties. Lets standardize on
'sram' as that is what TI already uses.

Rob
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