On Mon, Jun 24, 2019 at 3:39 PM Suman Anna [off-list ref] wrote:

Hi Jassi,

On 6/4/19 12:01 PM, Suman Anna wrote:

quoted

Hi Jassi,

The following series adds the support for the Mailbox IP present
within the Main NavSS module on the newer TI K3 AM65x and J721E SoCs.

The Mailbox IP is similar to the previous generation IP on OMAP SoCs
with a few differences:
 - Multiple IP instances from previous DRA7/AM57 family each form a
   cluster and are part of the same IP. The driver support will continue
   to be based on a cluster.
 - The IP is present within a Main NaVSS, and interrupts have to go
   through an Interrupt Router within Main NavSS before they reach the
   respective processor sub-system's interrupt controllers.
 - The register layout is mostly same, with difference in two registers

Support is added by enhancing the existing OMAP Mailbox driver to
support the K3 IP using a new compatible. The driver also has to be
adjusted to deal with the 32-bit mailbox payloads vs the 64-bit
pointers used by the Mailbox API on these Arm v8 platforms.

DT nodes will be posted separately once the binding is acked.

Can you please pick this series up for 5.3 merge window if you do not
have any comments.

I will. Usually I leave the code to cook in the open for as long as
possible, more so when no acks are coming.
Cheers!