On Sun, May 26, 2019 at 10:07:50AM +0530, Vidya Sagar wrote:
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar <redacted>
---
Changes since [v7]:
* Addressed review comments from Thierry
Changes since [v6]:
* Removed code around "nvidia,disable-aspm-states" DT property
* Refactored code to remove code duplication
Changes since [v5]:
* Addressed review comments from Thierry
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
* Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios'
* Removed .runtime_suspend() & .runtime_resume() implementations
Changes since [v1]:
* Made CONFIG_PCIE_TEGRA194 as 'm' by default from its previous 'y' state
* Modified code as per changes made to DT documentation
* Refactored code to address Bjorn & Thierry's review comments
* Added goto to avoid recursion in tegra_pcie_dw_host_init() API
* Merged .scan_bus() of dw_pcie_host_ops implementation to tegra_pcie_dw_host_init() API
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1621 ++++++++++++++++++++
3 files changed, 1632 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
Acked-by: Thierry Reding <redacted>