Thread (2 messages) 2 messages, 1 author, 2019-03-29
DORMANTno replies REVIEWED: 7 (7M)
Revisions (4)
  1. v2 [diff vs current]
  2. v3 [diff vs current]
  3. v4 [diff vs current]
  4. v5 current

[PATCH v5 2/2] dt-bindings: i2c: I2C binding for Mellanox BlueField SoC

From: Khalil Blaiech <hidden>
Date: 2019-03-29 19:40:41
Subsystem: i2c subsystem host drivers, open firmware and flattened device tree bindings, the rest · Maintainers: Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds

Added device tree bindings documentation for Mellanox BlueField
I2C SMBus controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Khalil Blaiech <redacted>
---
 .../devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
new file mode 100644
index 0000000..3478bb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt
@@ -0,0 +1,29 @@
+Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs
+
+Required Properties:
+- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2".
+
+- reg : address offset and length of the device registers. The
+	registers consist of the following set of resources:
+		1) Smbus block registers.
+		2) Cause master registers.
+		3) Cause slave registers.
+
+- interrupts : interrupt number.
+
+Optional Properties:
+
+- clock-frequency : bus frequency used to configure timing registers;
+			allowed values are 100000, 400000 and 1000000;
+			those are expressed in Hz. Default is 100000.
+
+Example:
+
+i2c@2804000 {
+	compatible = "mellanox,i2c-mlxbf1";
+	reg =	<0x02804000 0x800>,
+		<0x02801200 0x020>,
+		<0x02801260 0x020>;
+	interrupts = <57>;
+	clock-frequency = <100000>;
+};
-- 
2.1.2
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