[PATCH v11 23/27] MIPS: CI20: Reduce system timer and clocksource to 3 MHz
From: Paul Cercueil <paul@crapouillou.net>
Date: 2019-03-27 23:18:08
Also in:
linux-clk, linux-doc, linux-mips, linux-pwm, linux-watchdog, lkml
Subsystem:
ingenic jz47xx socs, mips, the rest · Maintainers:
Paul Cercueil, Thomas Bogendoerfer, Linus Torvalds
The default clock (48 MHz) is too fast for the system timer. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Mathieu Malaterre <redacted> Tested-by: Artur Rojek <redacted> --- arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 4f7b1fa31cf5..30b01cfaaf5a 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts@@ -238,3 +238,9 @@ bias-disable; }; }; + +&tcu { + /* 3 MHz for the system timer and clocksource */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; + assigned-clock-rates = <3000000>, <3000000>; +};
--
2.11.0