[PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors
From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Date: 2019-03-11 09:32:57
Also in:
linux-arm-kernel, linux-pci, lkml
Subsystem:
pci driver for mobiveil pcie ip, pci native host bridge and endpoint drivers, pci subsystem, the rest · Maintainers:
Karthikeyan Mitran, Hou Zhiqiang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Linus Torvalds
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> As there are some Byte and Half-Work width registers in PCIe configuration space, add Byte and Half-Word width register accessors. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <redacted> --- V4: - no change .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 81685840b378..933c2f34bc52 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h@@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) return csr_read(pcie, off, 0x4); } +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x2); +} + +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x1); +} + static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) { csr_write(pcie, val, off, 0x4); } +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) +{ + csr_write(pcie, val, off, 0x2); +} + +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) +{ + csr_write(pcie, val, off, 0x1); +} + #endif /* _PCIE_MOBIVEIL_H */
--
2.17.1