On Fri, 1 Feb 2019 07:07:40 +0000
[off-list ref] wrote:

quoted

quoted

 #define QSPI_IFR_TFRTYP_MASK            GENMASK(13, 12)
 #define QSPI_IFR_TFRTYP_TRSFR_READ      (0 << 12)
 #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM  (1 << 12)  

Looks like the read/write flag is on bit 13. Can we just add  

for sama5d2 only

Feel free to prefix macros with the SoC name to make it clear:

#define QSPI_IFR_SAMA5D2_WRITE_TRSFR		BIT(13)

quoted

#define QSPI_IFR_TFRTYP_TRSFR_WRITE	BIT(13)

and drop all others def? This way the implementation is consistent
between sam9x60 and sama5d2.  

BIT(13) has no meaning for sam9x60. I can drop the macros with zero value for
sama5d2 in a separate patch.

quoted

quoted

+#define QSPI_IFR_APBTFRTYP_READ		BIT(24)

And this one would be

define QSPI_IFR_SAM9X60_READ_TRSFR		BIT(24)

quoted

quoted

 
 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
 #define QSPI_SMR_SCREN                  BIT(0)

@@ -137,16 +144,37 @@
 #define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
 
 
+/* Describes register values. */
+struct atmel_qspi_cfg {
+	u32 icr;
+	u32 iar;
+	u32 ifr;
+};
+
+struct atmel_qspi_caps;
+
 struct atmel_qspi {
 	void __iomem		*regs;
 	void __iomem		*mem;
 	struct clk		*clk;  

Can we rename that on pclk?  

will rename it, together with the support for unnamed clock of sama5d2 in a separate
patch. The dt-bindings patch that imposes "pclk" for sama5d2 should be separated too.

Sounds good.