[PATCH 01/13] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
From: Jorge Ramirez-Ortiz <hidden>
Date: 2018-12-17 09:47:49
Also in:
linux-arm-kernel, linux-clk, lkml
Subsystem:
arm/qualcomm mailing list, common clk framework, qualcomm clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Bjorn Andersson, Linus Torvalds
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel <redacted> Signed-off-by: Niklas Cassel <redacted> Signed-off-by: Jorge Ramirez-Ortiz <redacted> --- drivers/clk/qcom/gcc-qcs404.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 64da032..833436a 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c@@ -304,10 +304,16 @@ static struct clk_alpha_pll gpll0_out_main = { }, }; +static const struct pll_vco gpll0_ao_out_vco[] = { + { 800000000, 800000000, 0 }, +}; + static struct clk_alpha_pll gpll0_ao_out_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .flags = SUPPORTS_FSM_MODE, + .vco_table = gpll0_ao_out_vco, + .num_vco = ARRAY_SIZE(gpll0_ao_out_vco), .clkr = { .enable_reg = 0x45000, .enable_mask = BIT(0),
--
2.7.4