Quoting Govind Singh (2018-10-12 02:40:42)

Add support for the WCSS QDSP clock control used on qcs404
based devices. This would allow wcss remoteproc driver to
control the required WCSS QDSP clock/reset controls to
bring the subsystem out of reset and shutdown the WCSS QDSP.

Signed-off-by: Govind Singh <redacted>
---

This needs to be sent to the clk mailing list and maintainers.

Why?

+       .clkr = {
+               .enable_reg = 0x38,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "q6ss_xo_clk",
+                       .ops = &clk_branch2_ops,
+                       .flags = CLK_IGNORE_UNUSED,
+               },
+       },
+};
+
+static struct clk_branch q6ss_slp_clk = {
+       .halt_reg = 0x3c,
+       .halt_check = BRANCH_HALT_SKIP,

Ditto. Please add a comment.

+       .clkr = {
+               .enable_reg = 0x3c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "q6ss_slp_clk",
+                       .ops = &clk_branch2_ops,
+                       .flags = CLK_IGNORE_UNUSED,
+               },
+       },
+};
+
+static struct clk_branch q6sstop_q6ss_gfmux_clk_src = {
+       .halt_reg = 0x20,
+       .halt_check = BRANCH_HALT_SKIP,
+       .clkr = {
+               .enable_reg = 0x20,
+               .enable_mask = (BIT(1) | BIT(3) | BIT(8)),

Drop useless parenthesis please. And this is actually three clks in one?

+               .hw.init = &(struct clk_init_data){
+                       .name = "q6sstop_q6ss_gfmux_clk_src",
+                       .ops = &clk_branch2_ops,
+                       .flags = CLK_IGNORE_UNUSED,

Why? Please explain with comment, etc.

+               },
+       },
+};
+
+static struct regmap_config wcss_regmap_config = {
+       .reg_bits       = 32,
+       .reg_stride     = 4,
+       .val_bits       = 32,
+       .fast_io        = true,

max register? Or that gets set later on somewhere?

+};
+
+static struct clk_regmap *wcss_q6sstop_qcs405_clocks[] = {
+       [WCSS_AHBFABRIC_CBCR_CLK] = &lcc_ahbfabric_cbc_clk.clkr,
+       [WCSS_AHBS_CBCR_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr,
+       [WCSS_TCM_CBCR_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr,
+       [WCSS_AHBM_CBCR_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr,
+       [WCSS_AXIM_CBCR_CLK] = &lcc_q6ss_axim_cbc_clk.clkr,
+       [WCSS_BCR_CBCR_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr,
+};
+
+static const struct qcom_reset_map qdsp6ss_qcs405_resets[] = {
+       [Q6SSTOP_QDSP6SS_RESET] = {0x14, 0},
+       [Q6SSTOP_QDSP6SS_CORE_RESET] = {0x14, 1},
+       [Q6SSTOP_QDSP6SS_BUS_RESET] = {0x14, 2},
+};
+
+static const struct qcom_reset_map q6sstop_qcs405_resets[] = {
+       [Q6SSTOP_BCR_RESET] = {0x6000},
+};
+
+static const struct qcom_cc_desc wcss_q6sstop_qcs405_desc = {
+       .config = &wcss_regmap_config,
+       .clks = wcss_q6sstop_qcs405_clocks,
+       .num_clks = ARRAY_SIZE(wcss_q6sstop_qcs405_clocks),
+       .resets = q6sstop_qcs405_resets,
+       .num_resets = ARRAY_SIZE(q6sstop_qcs405_resets),
+};
+
+static struct clk_regmap *wcnss_tcsr_qcs405_clocks[] = {
+       [WCSS_LCC_CBCR_CLK] = &wcss_lcc_csr_cbcr_clk.clkr,
+};
+
+static const struct qcom_cc_desc wcnss_tcsr_qcs405_desc = {
+       .config = &wcss_regmap_config,
+       .clks = wcnss_tcsr_qcs405_clocks,
+       .num_clks = ARRAY_SIZE(wcnss_tcsr_qcs405_clocks),
+};
+
+static struct clk_regmap *wcnss_qdsp6ss_qcs405_clocks[] = {
+       [WCSS_QDSP6SS_XO_CBCR_CLK] = &q6ss_xo_clk.clkr,
+       [WCSS_QDSP6SS_SLEEP_CBCR_CLK] = &q6ss_slp_clk.clkr,
+       [WCSS_QDSP6SS_GFMMUX_CLK] = &q6sstop_q6ss_gfmux_clk_src.clkr,
+};
+
+static const struct qcom_cc_desc wcnss_qdsp6ss_qcs405_desc = {
+       .config = &wcss_regmap_config,
+       .clks = wcnss_qdsp6ss_qcs405_clocks,
+       .num_clks = ARRAY_SIZE(wcnss_qdsp6ss_qcs405_clocks),
+       .resets = qdsp6ss_qcs405_resets,
+       .num_resets = ARRAY_SIZE(qdsp6ss_qcs405_resets),
+};
+
+static int wcss_clocks_qcs405_probe(struct platform_device *pdev, int index,
+                                   const struct qcom_cc_desc *desc)
+{
+       struct regmap *regmap;
+       struct resource *res;
+       void __iomem *base;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+       base = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(base))
+               return -ENOMEM;
+
+       regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
+       if (IS_ERR(regmap))
+               return PTR_ERR(regmap);
+
+       return qcom_cc_really_probe(pdev, desc, regmap);
+}
+
+/* WCSS CC clock controller */

Please drop the obvious comment!

+static const struct of_device_id wcss_cc_qcs405_match_table[] = {
+       { .compatible = "qcom,qcs405-wcsscc" },
+       { }
+};
+MODULE_DEVICE_TABLE(of, wcss_cc_qcs405_match_table);
+
+static int wcss_cc_qcs405_probe(struct platform_device *pdev)
+{
+       const struct qcom_cc_desc *desc;
+       int ret;
+
+       wcss_regmap_config.name = "wcss_q6sstop";
+       desc = &wcss_q6sstop_qcs405_desc;
+
+       ret = wcss_clocks_qcs405_probe(pdev, 0, desc);
+       if (ret)
+               return ret;
+
+       wcss_regmap_config.name = "wcnss_tcsr";
+       desc = &wcnss_tcsr_qcs405_desc;
+
+       ret = wcss_clocks_qcs405_probe(pdev, 1, desc);
+       if (ret)
+               return ret;
+
+       wcss_regmap_config.name = "wcss_qdsp6ss";
+       desc = &wcnss_qdsp6ss_qcs405_desc;
+
+       return wcss_clocks_qcs405_probe(pdev, 2, desc);
+}

And this is the second clk driver in qcom land to do this, so we need to
add this to style of clk driver to clk/qcom/common.c