[PATCH RFC v1 8/8] arm64: dtsi: sdm845: Add cpu power domain support
From: Raju P.L.S.S.S.N <hidden>
Date: 2018-10-10 21:22:19
Also in:
linux-arm-msm, linux-pm, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
Add cpu power domain support Signed-off-by: Raju P.L.S.S.S.N <redacted> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d3662a8..aadaa20 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi@@ -96,6 +96,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + power-domains = <&cpu_pd>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -111,6 +112,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&L2_100>; + power-domains = <&cpu_pd>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -123,6 +125,7 @@ reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&L2_200>; + power-domains = <&cpu_pd>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -135,6 +138,7 @@ reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&L2_300>; + power-domains = <&cpu_pd>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -147,6 +151,7 @@ reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&L2_400>; + power-domains = <&cpu_pd>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -159,6 +164,7 @@ reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&L2_500>; + power-domains = <&cpu_pd>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -171,6 +177,7 @@ reg = <0x0 0x600>; enable-method = "psci"; next-level-cache = <&L2_600>; + power-domains = <&cpu_pd>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -183,6 +190,7 @@ reg = <0x0 0x700>; enable-method = "psci"; next-level-cache = <&L2_700>; + power-domains = <&cpu_pd>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>;
@@ -1170,6 +1178,11 @@ <WAKE_TCS 3>, <CONTROL_TCS 1>; + cpu_pd: power-domain-controller { + compatible = "qcom,cpu-pm-domain"; + #power-domain-cells = <0>; + }; + rpmhcc: clock-controller { compatible = "qcom,sdm845-rpmh-clk"; #clock-cells = <1>;
--
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