On Tue, Aug 21, 2018 at 08:58:30AM +0200, Sascha Hauer wrote:

On Mon, Aug 20, 2018 at 10:16:06AM +0300, Abel Vesa wrote:

quoted

+
+	val |= (u32)value << divider->shift;
+	val |= (u32)value << PCG_DIV_SHIFT;
+	clk_writel(val, divider->reg);
+
+	spin_unlock_irqrestore(divider->lock, flags);
+
+	return 0;
+}

Have you tested this works? I thought those are two cascaded dividers
and you program both to the same value. Normally you would have to
calculate individual values for each divider which together give you the
desired output rate.

My bad. Haven't properly tested it since there is no actual driver that calls
set_rate on any of those clocks at this point. Sorry about that. I'll send
another version today, where I've implemented it as I should've done from the
start and I've tested it by explicitly calling the set_rate and read the value
with clk_get_rate to make sure it's fine.
 

Sascha

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