-----Original Message-----
From: Manish Narani [mailto:manish.narani@xilinx.com]
Sent: Saturday, August 4, 2018 2:56 PM
To: robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
will.deacon@arm.com; Michal Simek [off-list ref]; bp@alien8.de;
mchehab@kernel.org; mdf@kernel.org; Edgar Iglesias [off-list ref];
Shubhrajyoti Datta [off-list ref]; Naga Sureshkumar Relli
[off-list ref]; Bharat Kumar Gogada [off-list ref];
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Cc: Srinivas Goud <redacted>; Anirudha Sarangi
[off-list ref]; linux-kernel@vger.kernel.org;
devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
edac@vger.kernel.org; Manish Narani [off-list ref]
Subject: [PATCH v4 4/4] arm64: zynqmp: Add DDRC node

This patch adds ddrc memory controller node in dts. The size mentioned in dts
is 0x30000, because we need to access DDR_QOS INTR registers located at
fd090208 from this driver.

Signed-off-by: Manish Narani <redacted>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi

b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a091e6f..7d6a3cf 100644

--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi

@@ -355,6 +355,13 @@
 			xlnx,bus-width = <64>;
 		};

+		mc: memory-controller@fd070000 {
+			compatible = "xlnx,zynqmp-ddrc-2.40a";
+			reg = <0x0 0xfd070000 0x0 0x30000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 112 4>;
+		};
+
 		gem0: ethernet@ff0b0000 {
 			compatible = "cdns,zynqmp-gem", "cdns,gem";
 			status = "disabled";
--

2.1.1