[PATCH v2 12/17] dmaengine: dma-jz4780: Set DTCn register explicitly
From: Paul Cercueil <paul@crapouillou.net>
Date: 2018-07-18 18:21:04
Also in:
linux-mips, lkml
Subsystem:
dma generic offload engine subsystem, ingenic jz47xx socs, the rest · Maintainers:
Vinod Koul, Paul Cercueil, Linus Torvalds
From: Daniel Silsby <redacted> Normally, we wouldn't set the channel transfer count register directly when using descriptor-driven transfers. However, there is no harm in doing so, and it allows jz4780_dma_desc_residue() to report the correct residue of an ongoing transfer, no matter when it is called. Signed-off-by: Daniel Silsby <redacted> Tested-by: Mathieu Malaterre <redacted> --- drivers/dma/dma-jz4780.c | 9 +++++++++ 1 file changed, 9 insertions(+) v2: No change
diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
index cc2a86844db4..78849131c81d 100644
--- a/drivers/dma/dma-jz4780.c
+++ b/drivers/dma/dma-jz4780.c@@ -530,6 +530,15 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT, jzchan->transfer_type); + /* + * Set the transfer count. This is redundant for a descriptor-driven + * transfer. However, there can be a delay between the transfer start + * time and when DTCn reg contains the new transfer count. Setting + * it explicitly ensures residue is computed correctly at all times. + */ + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC, + jzchan->desc->desc[jzchan->curr_hwdesc].dtc); + /* Write descriptor address and initiate descriptor fetch. */ desc_phys = jzchan->desc->desc_phys + (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
--
2.11.0