-----Original Message-----
From: Abel Vesa
Sent: Wednesday, June 20, 2018 8:24 PM
To: Lucas Stach <l.stach@pengutronix.de>; A.s. Dong
[off-list ref]
Cc: linux-gpio@vger.kernel.org; dl-linux-imx <redacted>; Shawn
Guo [off-list ref]; Pengutronix Kernel Team
[off-list ref]; Linus Walleij [off-list ref]; Rob
Herring [off-list ref]; Mark Rutland [off-list ref];
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Abel Vesa
[off-list ref]; Abel Vesa [off-list ref]
Subject: [PATCH v4 1/2] dt-bindings: add binding for i.MX8MQ IOMUXC

This adds the binding for the i.MX8MQ pin controller, in the same fashion as
earlier i.MX SoCs.

Signed-off-by: Abel Vesa <redacted>
---
 .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt        | 29
++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt

b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
new file mode 100644
index 0000000..f11a3f0

--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt

@@ -0,0 +1,29 @@
+* Freescale IMX8MQ IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this
+directory for common binding part and usage.
+
+Required properties:
+- compatible: "fsl,imx8mq-iomuxc"
+- fsl,pins: each entry consists of 6 integers and represents the mux
+and config
+  setting for one pin.  The first 5 integers <mux_reg conf_reg
+input_reg mux_val
+  input_val> are specified using a PIN_FUNC_ID macro, which can be
+found in
+  imx8mq-pinfunc.h under device tree source folder.  The last integer
+CONFIG is
+  the pad setting value like pull-up on this pin.  Please refer to
+i.MX8M Quad
+  Reference Manual for detailed CONFIG settings.
+
+Examples:
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&iomuxc {
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX

0x49
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
0x49
+		>;
+	};
+};