Hi

On Sat, Jun 2, 2018 at 3:48 PM, Fabio Estevam [off-list ref] wrote:

Hi Stefan,

On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren [off-list ref] wrote:

quoted

quoted

--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h

@@ -242,20 +242,25 @@
 #define IMX6UL_CLK_CKO2_PODF         229
 #define IMX6UL_CLK_CKO2                      230
 #define IMX6UL_CLK_CKO                       231
+#define IMX6UL_CLK_GPIO1             232
+#define IMX6UL_CLK_GPIO2             233
+#define IMX6UL_CLK_GPIO3             234
+#define IMX6UL_CLK_GPIO4             235
+#define IMX6UL_CLK_GPIO5             236

this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.

Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new
clo01 and clo2 controlled
by CCOSR") which did the same reordering.

ull is a preatty new platform so one board was listed. Are you sure
that we need?

Michael

Thanks

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| Michael Nazzareno Trimarchi                     Amarula Solutions BV |
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